00001 /**********************************************************************************************************************\ 00002 00003 C++ library for Atmel AVR microcontrollers 00004 Copyright (C) 2007 Lauri Kirikal, Mikk Leini, Rasmus Raag, MTU TTU Robotiklubi 00005 00006 This program is free software; you can redistribute it and/or 00007 modify it under the terms of the GNU General Public License 00008 as published by the Free Software Foundation; either version 2 00009 of the License, or (at your option) any later version. 00010 00011 This program is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program; if not, write to the Free Software 00018 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00019 00020 See http://creativecommons.org/licenses/GPL/2.0/ 00021 00022 MTU TTU Robotiklubi http://www.robotiklubi.ee robotiklubi@gmail.com 00023 Lauri Kirikal laurikirikal@gmail.com 00024 Mikk Leini mikk.leini@gmail.com 00025 00026 \**********************************************************************************************************************/ 00027 00028 #ifndef __AVR_CPP_ATMEGA8515_IO_H__ 00029 #define __AVR_CPP_ATMEGA8515_IO_H__ 00030 00031 #if defined(__DOXYGEN__) && !defined(__AVR_CPP_IO_H__) 00032 #include <avr/cpp/IO.h> 00033 #endif 00034 00035 #ifndef __AVR_CPP_IO_H__ 00036 #error "Include <avr/cpp/IO.h> instead of <avr/cpp/atmega8515/IO.h>." 00037 #else 00038 00039 00040 /**********************************************************************************************************************\ 00041 00042 atmega8515 registers, bits and ports declarations. 00043 This file is generated. Do not modify manually. 00044 00045 \**********************************************************************************************************************/ 00046 00047 // Registers 00048 namespace AVRCpp 00049 { 00050 __DECLARE_8BIT_REGISTER__(SREG); 00051 __DECLARE_8BIT_REGISTER__(SPH); 00052 __DECLARE_8BIT_REGISTER__(SPL); 00053 __DECLARE_8BIT_REGISTER__(GICR); 00054 __DECLARE_8BIT_REGISTER__(GIFR); 00055 __DECLARE_8BIT_REGISTER__(TIMSK); 00056 __DECLARE_8BIT_REGISTER__(TIFR); 00057 __DECLARE_8BIT_REGISTER__(SPMCR); 00058 __DECLARE_8BIT_REGISTER__(EMCUCR); 00059 __DECLARE_8BIT_REGISTER__(MCUCR); 00060 __DECLARE_8BIT_REGISTER__(MCUCSR); 00061 __DECLARE_8BIT_REGISTER__(TCCR0); 00062 __DECLARE_8BIT_REGISTER__(TCNT0); 00063 __DECLARE_8BIT_REGISTER__(OCR0); 00064 __DECLARE_8BIT_REGISTER__(SFIOR); 00065 __DECLARE_8BIT_REGISTER__(TCCR1A); 00066 __DECLARE_8BIT_REGISTER__(TCCR1B); 00067 __DECLARE_8BIT_REGISTER__(TCNT1H); 00068 __DECLARE_8BIT_REGISTER__(TCNT1L); 00069 __DECLARE_8BIT_REGISTER__(OCR1AH); 00070 __DECLARE_8BIT_REGISTER__(OCR1AL); 00071 __DECLARE_8BIT_REGISTER__(OCR1BH); 00072 __DECLARE_8BIT_REGISTER__(OCR1BL); 00073 __DECLARE_8BIT_REGISTER__(ICR1H); 00074 __DECLARE_8BIT_REGISTER__(ICR1L); 00075 __DECLARE_8BIT_REGISTER__(WDTCR); 00076 __DECLARE_8BIT_REGISTER__(UBRRH); 00077 __DECLARE_8BIT_REGISTER__(UCSRC); 00078 __DECLARE_8BIT_REGISTER__(EEARH); 00079 __DECLARE_8BIT_REGISTER__(EEARL); 00080 __DECLARE_8BIT_REGISTER__(EEDR); 00081 __DECLARE_8BIT_REGISTER__(EECR); 00082 __DECLARE_8BIT_REGISTER__(PORTA); 00083 __DECLARE_8BIT_REGISTER__(DDRA); 00084 __DECLARE_8BIT_REGISTER__(PINA); 00085 __DECLARE_8BIT_REGISTER__(PORTB); 00086 __DECLARE_8BIT_REGISTER__(DDRB); 00087 __DECLARE_8BIT_REGISTER__(PINB); 00088 __DECLARE_8BIT_REGISTER__(PORTC); 00089 __DECLARE_8BIT_REGISTER__(DDRC); 00090 __DECLARE_8BIT_REGISTER__(PINC); 00091 __DECLARE_8BIT_REGISTER__(PORTD); 00092 __DECLARE_8BIT_REGISTER__(DDRD); 00093 __DECLARE_8BIT_REGISTER__(PIND); 00094 __DECLARE_8BIT_REGISTER__(SPDR); 00095 __DECLARE_8BIT_REGISTER__(SPSR); 00096 __DECLARE_8BIT_REGISTER__(SPCR); 00097 __DECLARE_8BIT_REGISTER__(UDR); 00098 __DECLARE_8BIT_REGISTER__(UCSRA); 00099 __DECLARE_8BIT_REGISTER__(UCSRB); 00100 __DECLARE_8BIT_REGISTER__(UBRRL); 00101 __DECLARE_8BIT_REGISTER__(ACSR); 00102 __DECLARE_8BIT_REGISTER__(PORTE); 00103 __DECLARE_8BIT_REGISTER__(DDRE); 00104 __DECLARE_8BIT_REGISTER__(PINE); 00105 __DECLARE_8BIT_REGISTER__(OSCCAL); 00106 __DECLARE_16BIT_REGISTER__(SP); 00107 __DECLARE_16BIT_REGISTER__(TCNT1); 00108 __DECLARE_16BIT_REGISTER__(OCR1A); 00109 __DECLARE_16BIT_REGISTER__(OCR1B); 00110 __DECLARE_16BIT_REGISTER__(ICR1); 00111 00112 } // namespace AVRCpp 00113 00114 00115 // SREG 00116 #define _SREG_I 0x80 00117 #define _SREG_T 0x40 00118 #define _SREG_H 0x20 00119 #define _SREG_S 0x10 00120 #define _SREG_V 0x8 00121 #define _SREG_N 0x4 00122 #define _SREG_Z 0x2 00123 #define _SREG_C 0x1 00124 00125 // SPH 00126 #define _SP15 0x80 00127 #define _SP14 0x40 00128 #define _SP13 0x20 00129 #define _SP12 0x10 00130 #define _SP11 0x8 00131 #define _SP10 0x4 00132 #define _SP9 0x2 00133 #define _SP8 0x1 00134 00135 // SPL 00136 #define _SP7 0x80 00137 #define _SP6 0x40 00138 #define _SP5 0x20 00139 #define _SP4 0x10 00140 #define _SP3 0x8 00141 #define _SP2 0x4 00142 #define _SP1 0x2 00143 #define _SP0 0x1 00144 00145 // GICR 00146 #define _INT1 0x80 00147 #define _INT0 0x40 00148 #define _INT2 0x20 00149 #define _IVSEL 0x2 00150 #define _IVCE 0x1 00151 00152 // GIFR 00153 #define _INTF1 0x80 00154 #define _INTF0 0x40 00155 #define _INTF2 0x20 00156 00157 // TIMSK 00158 #define _TOIE1 0x80 00159 #define _OCIE1A 0x40 00160 #define _OCIE1B 0x20 00161 #define _TICIE1 0x8 00162 #define _TOIE0 0x2 00163 #define _OCIE0 0x1 00164 00165 // TIFR 00166 #define _TOV1 0x80 00167 #define _OCF1A 0x40 00168 #define _OCF1B 0x20 00169 #define _ICF1 0x8 00170 #define _TOV0 0x2 00171 #define _OCF0 0x1 00172 00173 // SPMCR 00174 #define _SPMIE 0x80 00175 #define _RWWSB 0x40 00176 #define _RWWSRE 0x10 00177 #define _BLBSET 0x8 00178 #define _PGWRT 0x4 00179 #define _PGERS 0x2 00180 #define _SPMEN 0x1 00181 00182 // EMCUCR 00183 #define _SM0 0x80 00184 #define _SRL2 0x40 00185 #define _SRL1 0x20 00186 #define _SRL0 0x10 00187 #define _SRW01 0x8 00188 #define _SRW00 0x4 00189 #define _SRW11 0x2 00190 #define _ISC2 0x1 00191 00192 // MCUCR 00193 #define _SRE 0x80 00194 #define _SRW10 0x40 00195 #define _SE 0x20 00196 #define _SM1 0x10 00197 #define _ISC11 0x8 00198 #define _ISC10 0x4 00199 #define _ISC01 0x2 00200 #define _ISC00 0x1 00201 00202 // MCUCSR 00203 #define _SM2 0x20 00204 #define _WDRF 0x8 00205 #define _BORF 0x4 00206 #define _EXTRF 0x2 00207 #define _PORF 0x1 00208 00209 // TCCR0 00210 #define _FOC0 0x80 00211 #define _WGM00 0x40 00212 #define _COM01 0x20 00213 #define _COM00 0x10 00214 #define _WGM01 0x8 00215 #define _CS02 0x4 00216 #define _CS01 0x2 00217 #define _CS00 0x1 00218 00219 // SFIOR 00220 #define _XMBK 0x40 00221 #define _XMM2 0x20 00222 #define _XMM1 0x10 00223 #define _XMM0 0x8 00224 #define _PUD 0x4 00225 #define _PSR10 0x1 00226 00227 // TCCR1A 00228 #define _COM1A1 0x80 00229 #define _COM1A0 0x40 00230 #define _COM1B1 0x20 00231 #define _COM1B0 0x10 00232 #define _FOC1A 0x8 00233 #define _FOC1B 0x4 00234 #define _WGM11 0x2 00235 #define _WGM10 0x1 00236 00237 // TCCR1B 00238 #define _ICNC1 0x80 00239 #define _ICES1 0x40 00240 #define _WGM13 0x10 00241 #define _WGM12 0x8 00242 #define _CS12 0x4 00243 #define _CS11 0x2 00244 #define _CS10 0x1 00245 00246 // WDTCR 00247 #define _WDCE 0x10 00248 #define _WDE 0x8 00249 #define _WDP2 0x4 00250 #define _WDP1 0x2 00251 #define _WDP0 0x1 00252 00253 // UCSRC 00254 #define _URSEL 0x80 00255 #define _UMSEL 0x40 00256 #define _UPM1 0x20 00257 #define _UPM0 0x10 00258 #define _USBS 0x8 00259 #define _UCSZ1 0x4 00260 #define _UCSZ0 0x2 00261 #define _UCPOL 0x1 00262 00263 // EEARH 00264 #define _EEAR8 0x1 00265 00266 // EECR 00267 #define _EERIE 0x8 00268 #define _EEMWE 0x4 00269 #define _EEWE 0x2 00270 #define _EERE 0x1 00271 00272 // PORTA 00273 #define _PA7 0x80 00274 #define _PA6 0x40 00275 #define _PA5 0x20 00276 #define _PA4 0x10 00277 #define _PA3 0x8 00278 #define _PA2 0x4 00279 #define _PA1 0x2 00280 #define _PA0 0x1 00281 00282 // DDRA 00283 #define _DDA7 0x80 00284 #define _DDA6 0x40 00285 #define _DDA5 0x20 00286 #define _DDA4 0x10 00287 #define _DDA3 0x8 00288 #define _DDA2 0x4 00289 #define _DDA1 0x2 00290 #define _DDA0 0x1 00291 00292 // PINA 00293 #define _PINA7 0x80 00294 #define _PINA6 0x40 00295 #define _PINA5 0x20 00296 #define _PINA4 0x10 00297 #define _PINA3 0x8 00298 #define _PINA2 0x4 00299 #define _PINA1 0x2 00300 #define _PINA0 0x1 00301 00302 // PORTB 00303 #define _PB7 0x80 00304 #define _PB6 0x40 00305 #define _PB5 0x20 00306 #define _PB4 0x10 00307 #define _PB3 0x8 00308 #define _PB2 0x4 00309 #define _PB1 0x2 00310 #define _PB0 0x1 00311 00312 // DDRB 00313 #define _DDB7 0x80 00314 #define _DDB6 0x40 00315 #define _DDB5 0x20 00316 #define _DDB4 0x10 00317 #define _DDB3 0x8 00318 #define _DDB2 0x4 00319 #define _DDB1 0x2 00320 #define _DDB0 0x1 00321 00322 // PINB 00323 #define _PINB7 0x80 00324 #define _PINB6 0x40 00325 #define _PINB5 0x20 00326 #define _PINB4 0x10 00327 #define _PINB3 0x8 00328 #define _PINB2 0x4 00329 #define _PINB1 0x2 00330 #define _PINB0 0x1 00331 00332 // PORTC 00333 #define _PC7 0x80 00334 #define _PC6 0x40 00335 #define _PC5 0x20 00336 #define _PC4 0x10 00337 #define _PC3 0x8 00338 #define _PC2 0x4 00339 #define _PC1 0x2 00340 #define _PC0 0x1 00341 00342 // DDRC 00343 #define _DDC7 0x80 00344 #define _DDC6 0x40 00345 #define _DDC5 0x20 00346 #define _DDC4 0x10 00347 #define _DDC3 0x8 00348 #define _DDC2 0x4 00349 #define _DDC1 0x2 00350 #define _DDC0 0x1 00351 00352 // PINC 00353 #define _PINC7 0x80 00354 #define _PINC6 0x40 00355 #define _PINC5 0x20 00356 #define _PINC4 0x10 00357 #define _PINC3 0x8 00358 #define _PINC2 0x4 00359 #define _PINC1 0x2 00360 #define _PINC0 0x1 00361 00362 // PORTD 00363 #define _PD7 0x80 00364 #define _PD6 0x40 00365 #define _PD5 0x20 00366 #define _PD4 0x10 00367 #define _PD3 0x8 00368 #define _PD2 0x4 00369 #define _PD1 0x2 00370 #define _PD0 0x1 00371 00372 // DDRD 00373 #define _DDD7 0x80 00374 #define _DDD6 0x40 00375 #define _DDD5 0x20 00376 #define _DDD4 0x10 00377 #define _DDD3 0x8 00378 #define _DDD2 0x4 00379 #define _DDD1 0x2 00380 #define _DDD0 0x1 00381 00382 // PIND 00383 #define _PIND7 0x80 00384 #define _PIND6 0x40 00385 #define _PIND5 0x20 00386 #define _PIND4 0x10 00387 #define _PIND3 0x8 00388 #define _PIND2 0x4 00389 #define _PIND1 0x2 00390 #define _PIND0 0x1 00391 00392 // SPSR 00393 #define _SPIF 0x80 00394 #define _WCOL 0x40 00395 #define _SPI2X 0x1 00396 00397 // SPCR 00398 #define _SPIE 0x80 00399 #define _SPE 0x40 00400 #define _DORD 0x20 00401 #define _MSTR 0x10 00402 #define _CPOL 0x8 00403 #define _CPHA 0x4 00404 #define _SPR1 0x2 00405 #define _SPR0 0x1 00406 00407 // UCSRA 00408 #define _RXC 0x80 00409 #define _TXC 0x40 00410 #define _UDRE 0x20 00411 #define _FE 0x10 00412 #define _DOR 0x8 00413 #define _PE 0x4 00414 #define _U2X 0x2 00415 #define _MPCM 0x1 00416 00417 // UCSRB 00418 #define _RXCIE 0x80 00419 #define _TXCIE 0x40 00420 #define _UDRIE 0x20 00421 #define _RXEN 0x10 00422 #define _TXEN 0x8 00423 #define _UCSZ2 0x4 00424 #define _RXB8 0x2 00425 #define _TXB8 0x1 00426 00427 // ACSR 00428 #define _ACD 0x80 00429 #define _ACBG 0x40 00430 #define _ACO 0x20 00431 #define _ACI 0x10 00432 #define _ACIE 0x8 00433 #define _ACIC 0x4 00434 #define _ACIS1 0x2 00435 #define _ACIS0 0x1 00436 00437 // PORTE 00438 #define _PE2 0x4 00439 #define _PE1 0x2 00440 #define _PE0 0x1 00441 00442 // DDRE 00443 #define _DDE2 0x4 00444 #define _DDE1 0x2 00445 #define _DDE0 0x1 00446 00447 // PINE 00448 #define _PINE2 0x4 00449 #define _PINE1 0x2 00450 #define _PINE0 0x1 00451 00452 00453 // General ports 00454 namespace AVRCpp 00455 { 00456 __DECLARE_PORT__(A); 00457 __DECLARE_PORT__(B); 00458 __DECLARE_PORT__(C); 00459 __DECLARE_PORT__(D); 00460 __DECLARE_PORT__(E); 00461 00462 } // namespace AVRCpp 00463 00464 00465 /**********************************************************************************************************************/ 00466 00467 #endif // ifndef __AVR_CPP_IO_H__ 00468 #endif // ifndef __AVR_CPP_ATMEGA8515_IO_H__
1.5.2
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 MTÜ TTÜ Robotiklubi
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