00001 /**********************************************************************************************************************\ 00002 00003 C++ library for Atmel AVR microcontrollers 00004 Copyright (C) 2007 Lauri Kirikal, Mikk Leini, Rasmus Raag, MTU TTU Robotiklubi 00005 00006 This program is free software; you can redistribute it and/or 00007 modify it under the terms of the GNU General Public License 00008 as published by the Free Software Foundation; either version 2 00009 of the License, or (at your option) any later version. 00010 00011 This program is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program; if not, write to the Free Software 00018 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00019 00020 See http://creativecommons.org/licenses/GPL/2.0/ 00021 00022 MTU TTU Robotiklubi http://www.robotiklubi.ee robotiklubi@gmail.com 00023 Lauri Kirikal laurikirikal@gmail.com 00024 Mikk Leini mikk.leini@gmail.com 00025 00026 \**********************************************************************************************************************/ 00027 00028 #ifndef __AVR_CPP_ATMEGA8_IO_H__ 00029 #define __AVR_CPP_ATMEGA8_IO_H__ 00030 00031 #if defined(__DOXYGEN__) && !defined(__AVR_CPP_IO_H__) 00032 #include <avr/cpp/IO.h> 00033 #endif 00034 00035 #ifndef __AVR_CPP_IO_H__ 00036 #error "Include <avr/cpp/IO.h> instead of <avr/cpp/atmega8/IO.h>." 00037 #else 00038 00039 00040 /**********************************************************************************************************************\ 00041 00042 atmega8 registers, bits and ports declarations. 00043 This file is generated. Do not modify manually. 00044 00045 \**********************************************************************************************************************/ 00046 00047 // Registers 00048 namespace AVRCpp 00049 { 00050 __DECLARE_8BIT_REGISTER__(SREG); 00051 __DECLARE_8BIT_REGISTER__(SPH); 00052 __DECLARE_8BIT_REGISTER__(SPL); 00053 __DECLARE_8BIT_REGISTER__(GICR); 00054 __DECLARE_8BIT_REGISTER__(GIFR); 00055 __DECLARE_8BIT_REGISTER__(TIMSK); 00056 __DECLARE_8BIT_REGISTER__(TIFR); 00057 __DECLARE_8BIT_REGISTER__(SPMCR); 00058 __DECLARE_8BIT_REGISTER__(TWCR); 00059 __DECLARE_8BIT_REGISTER__(MCUCR); 00060 __DECLARE_8BIT_REGISTER__(MCUCSR); 00061 __DECLARE_8BIT_REGISTER__(TCCR0); 00062 __DECLARE_8BIT_REGISTER__(TCNT0); 00063 __DECLARE_8BIT_REGISTER__(OSCCAL); 00064 __DECLARE_8BIT_REGISTER__(SFIOR); 00065 __DECLARE_8BIT_REGISTER__(TCCR1A); 00066 __DECLARE_8BIT_REGISTER__(TCCR1B); 00067 __DECLARE_8BIT_REGISTER__(TCNT1H); 00068 __DECLARE_8BIT_REGISTER__(TCNT1L); 00069 __DECLARE_8BIT_REGISTER__(OCR1AH); 00070 __DECLARE_8BIT_REGISTER__(OCR1AL); 00071 __DECLARE_8BIT_REGISTER__(OCR1BH); 00072 __DECLARE_8BIT_REGISTER__(OCR1BL); 00073 __DECLARE_8BIT_REGISTER__(ICR1H); 00074 __DECLARE_8BIT_REGISTER__(ICR1L); 00075 __DECLARE_8BIT_REGISTER__(TCCR2); 00076 __DECLARE_8BIT_REGISTER__(TCNT2); 00077 __DECLARE_8BIT_REGISTER__(OCR2); 00078 __DECLARE_8BIT_REGISTER__(ASSR); 00079 __DECLARE_8BIT_REGISTER__(WDTCR); 00080 __DECLARE_8BIT_REGISTER__(UBRRH); 00081 __DECLARE_8BIT_REGISTER__(UCSRC); 00082 __DECLARE_8BIT_REGISTER__(EEARH); 00083 __DECLARE_8BIT_REGISTER__(EEARL); 00084 __DECLARE_8BIT_REGISTER__(EEDR); 00085 __DECLARE_8BIT_REGISTER__(EECR); 00086 __DECLARE_8BIT_REGISTER__(PORTB); 00087 __DECLARE_8BIT_REGISTER__(DDRB); 00088 __DECLARE_8BIT_REGISTER__(PINB); 00089 __DECLARE_8BIT_REGISTER__(PORTC); 00090 __DECLARE_8BIT_REGISTER__(DDRC); 00091 __DECLARE_8BIT_REGISTER__(PINC); 00092 __DECLARE_8BIT_REGISTER__(PORTD); 00093 __DECLARE_8BIT_REGISTER__(DDRD); 00094 __DECLARE_8BIT_REGISTER__(PIND); 00095 __DECLARE_8BIT_REGISTER__(SPDR); 00096 __DECLARE_8BIT_REGISTER__(SPSR); 00097 __DECLARE_8BIT_REGISTER__(SPCR); 00098 __DECLARE_8BIT_REGISTER__(UDR); 00099 __DECLARE_8BIT_REGISTER__(UCSRA); 00100 __DECLARE_8BIT_REGISTER__(UCSRB); 00101 __DECLARE_8BIT_REGISTER__(UBRRL); 00102 __DECLARE_8BIT_REGISTER__(ACSR); 00103 __DECLARE_8BIT_REGISTER__(ADMUX); 00104 __DECLARE_8BIT_REGISTER__(ADCSRA); 00105 __DECLARE_8BIT_REGISTER__(ADCH); 00106 __DECLARE_8BIT_REGISTER__(ADCL); 00107 __DECLARE_8BIT_REGISTER__(TWDR); 00108 __DECLARE_8BIT_REGISTER__(TWAR); 00109 __DECLARE_8BIT_REGISTER__(TWSR); 00110 __DECLARE_8BIT_REGISTER__(TWBR); 00111 __DECLARE_16BIT_REGISTER__(TCNT1); 00112 __DECLARE_16BIT_REGISTER__(OCR1A); 00113 __DECLARE_16BIT_REGISTER__(OCR1B); 00114 __DECLARE_16BIT_REGISTER__(ICR1); 00115 __DECLARE_16BIT_REGISTER__(ADC); 00116 00117 } // namespace AVRCpp 00118 00119 00120 // SREG 00121 #define _SREG_I 0x80 00122 #define _SREG_T 0x40 00123 #define _SREG_H 0x20 00124 #define _SREG_S 0x10 00125 #define _SREG_V 0x8 00126 #define _SREG_N 0x4 00127 #define _SREG_Z 0x2 00128 #define _SREG_C 0x1 00129 00130 // SPH 00131 #define _SP10 0x4 00132 #define _SP9 0x2 00133 #define _SP8 0x1 00134 00135 // SPL 00136 #define _SP7 0x80 00137 #define _SP6 0x40 00138 #define _SP5 0x20 00139 #define _SP4 0x10 00140 #define _SP3 0x8 00141 #define _SP2 0x4 00142 #define _SP1 0x2 00143 #define _SP0 0x1 00144 00145 // GICR 00146 #define _INT1 0x80 00147 #define _INT0 0x40 00148 #define _IVSEL 0x2 00149 #define _IVCE 0x1 00150 00151 // GIFR 00152 #define _INTF1 0x80 00153 #define _INTF0 0x40 00154 00155 // TIMSK 00156 #define _OCIE2 0x80 00157 #define _TOIE2 0x40 00158 #define _TICIE1 0x20 00159 #define _OCIE1A 0x10 00160 #define _OCIE1B 0x8 00161 #define _TOIE1 0x4 00162 #define _TOIE0 0x1 00163 00164 // TIFR 00165 #define _OCF2 0x80 00166 #define _TOV2 0x40 00167 #define _ICF1 0x20 00168 #define _OCF1A 0x10 00169 #define _OCF1B 0x8 00170 #define _TOV1 0x4 00171 #define _TOV0 0x1 00172 00173 // SPMCR 00174 #define _SPMIE 0x80 00175 #define _RWWSB 0x40 00176 #define _RWWSRE 0x10 00177 #define _BLBSET 0x8 00178 #define _PGWRT 0x4 00179 #define _PGERS 0x2 00180 #define _SPMEN 0x1 00181 00182 // TWCR 00183 #define _TWINT 0x80 00184 #define _TWEA 0x40 00185 #define _TWSTA 0x20 00186 #define _TWSTO 0x10 00187 #define _TWWC 0x8 00188 #define _TWEN 0x4 00189 #define _TWIE 0x1 00190 00191 // MCUCR 00192 #define _SE 0x80 00193 #define _SM2 0x40 00194 #define _SM1 0x20 00195 #define _SM0 0x10 00196 #define _ISC11 0x8 00197 #define _ISC10 0x4 00198 #define _ISC01 0x2 00199 #define _ISC00 0x1 00200 00201 // MCUCSR 00202 #define _WDRF 0x8 00203 #define _BORF 0x4 00204 #define _EXTRF 0x2 00205 #define _PORF 0x1 00206 00207 // TCCR0 00208 #define _CS02 0x4 00209 #define _CS01 0x2 00210 #define _CS00 0x1 00211 00212 // SFIOR 00213 #define _ACME 0x8 00214 #define _PUD 0x4 00215 #define _PSR2 0x2 00216 #define _PSR10 0x1 00217 00218 // TCCR1A 00219 #define _COM1A1 0x80 00220 #define _COM1A0 0x40 00221 #define _COM1B1 0x20 00222 #define _COM1B0 0x10 00223 #define _FOC1A 0x8 00224 #define _FOC1B 0x4 00225 #define _WGM11 0x2 00226 #define _WGM10 0x1 00227 00228 // TCCR1B 00229 #define _ICNC1 0x80 00230 #define _ICES1 0x40 00231 #define _WGM13 0x10 00232 #define _WGM12 0x8 00233 #define _CS12 0x4 00234 #define _CS11 0x2 00235 #define _CS10 0x1 00236 00237 // TCCR2 00238 #define _FOC2 0x80 00239 #define _WGM20 0x40 00240 #define _COM21 0x20 00241 #define _COM20 0x10 00242 #define _WGM21 0x8 00243 #define _CS22 0x4 00244 #define _CS21 0x2 00245 #define _CS20 0x1 00246 00247 // ASSR 00248 #define _AS2 0x8 00249 #define _TCN2UB 0x4 00250 #define _OCR2UB 0x2 00251 #define _TCR2UB 0x1 00252 00253 // WDTCR 00254 #define _WDCE 0x10 00255 #define _WDE 0x8 00256 #define _WDP2 0x4 00257 #define _WDP1 0x2 00258 #define _WDP0 0x1 00259 00260 // UCSRC 00261 #define _URSEL 0x80 00262 #define _UMSEL 0x40 00263 #define _UPM1 0x20 00264 #define _UPM0 0x10 00265 #define _USBS 0x8 00266 #define _UCSZ1 0x4 00267 #define _UCSZ0 0x2 00268 #define _UCPOL 0x1 00269 00270 // EEARH 00271 #define _EEAR8 0x1 00272 00273 // EEARL 00274 #define _EEAR7 0x80 00275 #define _EEAR6 0x40 00276 #define _EEAR5 0x20 00277 #define _EEAR4 0x10 00278 #define _EEAR3 0x8 00279 #define _EEAR2 0x4 00280 #define _EEAR1 0x2 00281 #define _EEAR0 0x1 00282 00283 // EECR 00284 #define _EERIE 0x8 00285 #define _EEMWE 0x4 00286 #define _EEWE 0x2 00287 #define _EERE 0x1 00288 00289 // PORTB 00290 #define _PB7 0x80 00291 #define _PB6 0x40 00292 #define _PB5 0x20 00293 #define _PB4 0x10 00294 #define _PB3 0x8 00295 #define _PB2 0x4 00296 #define _PB1 0x2 00297 #define _PB0 0x1 00298 00299 // DDRB 00300 #define _DDB7 0x80 00301 #define _DDB6 0x40 00302 #define _DDB5 0x20 00303 #define _DDB4 0x10 00304 #define _DDB3 0x8 00305 #define _DDB2 0x4 00306 #define _DDB1 0x2 00307 #define _DDB0 0x1 00308 00309 // PINB 00310 #define _PINB7 0x80 00311 #define _PINB6 0x40 00312 #define _PINB5 0x20 00313 #define _PINB4 0x10 00314 #define _PINB3 0x8 00315 #define _PINB2 0x4 00316 #define _PINB1 0x2 00317 #define _PINB0 0x1 00318 00319 // PORTC 00320 #define _PC6 0x40 00321 #define _PC5 0x20 00322 #define _PC4 0x10 00323 #define _PC3 0x8 00324 #define _PC2 0x4 00325 #define _PC1 0x2 00326 #define _PC0 0x1 00327 00328 // DDRC 00329 #define _DDC6 0x40 00330 #define _DDC5 0x20 00331 #define _DDC4 0x10 00332 #define _DDC3 0x8 00333 #define _DDC2 0x4 00334 #define _DDC1 0x2 00335 #define _DDC0 0x1 00336 00337 // PINC 00338 #define _PINC6 0x40 00339 #define _PINC5 0x20 00340 #define _PINC4 0x10 00341 #define _PINC3 0x8 00342 #define _PINC2 0x4 00343 #define _PINC1 0x2 00344 #define _PINC0 0x1 00345 00346 // PORTD 00347 #define _PD7 0x80 00348 #define _PD6 0x40 00349 #define _PD5 0x20 00350 #define _PD4 0x10 00351 #define _PD3 0x8 00352 #define _PD2 0x4 00353 #define _PD1 0x2 00354 #define _PD0 0x1 00355 00356 // DDRD 00357 #define _DDD7 0x80 00358 #define _DDD6 0x40 00359 #define _DDD5 0x20 00360 #define _DDD4 0x10 00361 #define _DDD3 0x8 00362 #define _DDD2 0x4 00363 #define _DDD1 0x2 00364 #define _DDD0 0x1 00365 00366 // PIND 00367 #define _PIND7 0x80 00368 #define _PIND6 0x40 00369 #define _PIND5 0x20 00370 #define _PIND4 0x10 00371 #define _PIND3 0x8 00372 #define _PIND2 0x4 00373 #define _PIND1 0x2 00374 #define _PIND0 0x1 00375 00376 // SPSR 00377 #define _SPIF 0x80 00378 #define _WCOL 0x40 00379 #define _SPI2X 0x1 00380 00381 // SPCR 00382 #define _SPIE 0x80 00383 #define _SPE 0x40 00384 #define _DORD 0x20 00385 #define _MSTR 0x10 00386 #define _CPOL 0x8 00387 #define _CPHA 0x4 00388 #define _SPR1 0x2 00389 #define _SPR0 0x1 00390 00391 // UCSRA 00392 #define _RXC 0x80 00393 #define _TXC 0x40 00394 #define _UDRE 0x20 00395 #define _FE 0x10 00396 #define _DOR 0x8 00397 #define _PE 0x4 00398 #define _U2X 0x2 00399 #define _MPCM 0x1 00400 00401 // UCSRB 00402 #define _RXCIE 0x80 00403 #define _TXCIE 0x40 00404 #define _UDRIE 0x20 00405 #define _RXEN 0x10 00406 #define _TXEN 0x8 00407 #define _UCSZ2 0x4 00408 #define _RXB8 0x2 00409 #define _TXB8 0x1 00410 00411 // ACSR 00412 #define _ACD 0x80 00413 #define _ACBG 0x40 00414 #define _ACO 0x20 00415 #define _ACI 0x10 00416 #define _ACIE 0x8 00417 #define _ACIC 0x4 00418 #define _ACIS1 0x2 00419 #define _ACIS0 0x1 00420 00421 // ADMUX 00422 #define _REFS1 0x80 00423 #define _REFS0 0x40 00424 #define _ADLAR 0x20 00425 #define _MUX3 0x8 00426 #define _MUX2 0x4 00427 #define _MUX1 0x2 00428 #define _MUX0 0x1 00429 00430 // ADCSRA 00431 #define _ADEN 0x80 00432 #define _ADSC 0x40 00433 #define _ADFR 0x20 00434 #define _ADIF 0x10 00435 #define _ADIE 0x8 00436 #define _ADPS2 0x4 00437 #define _ADPS1 0x2 00438 #define _ADPS0 0x1 00439 00440 // TWAR 00441 #define _TWA6 0x80 00442 #define _TWA5 0x40 00443 #define _TWA4 0x20 00444 #define _TWA3 0x10 00445 #define _TWA2 0x8 00446 #define _TWA1 0x4 00447 #define _TWA0 0x2 00448 #define _TWGCE 0x1 00449 00450 // TWSR 00451 #define _TWS7 0x80 00452 #define _TWS6 0x40 00453 #define _TWS5 0x20 00454 #define _TWS4 0x10 00455 #define _TWS3 0x8 00456 #define _TWPS1 0x2 00457 #define _TWPS0 0x1 00458 00459 00460 // General ports 00461 namespace AVRCpp 00462 { 00463 __DECLARE_PORT__(B); 00464 __DECLARE_PORT__(C); 00465 __DECLARE_PORT__(D); 00466 00467 } // namespace AVRCpp 00468 00469 00470 /**********************************************************************************************************************/ 00471 00472 #endif // ifndef __AVR_CPP_IO_H__ 00473 #endif // ifndef __AVR_CPP_ATMEGA8_IO_H__
1.5.2
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 MTÜ TTÜ Robotiklubi
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