00001 /**********************************************************************************************************************\ 00002 00003 C++ library for Atmel AVR microcontrollers 00004 Copyright (C) 2007 Lauri Kirikal, Mikk Leini, Rasmus Raag, MTU TTU Robotiklubi 00005 00006 This program is free software; you can redistribute it and/or 00007 modify it under the terms of the GNU General Public License 00008 as published by the Free Software Foundation; either version 2 00009 of the License, or (at your option) any later version. 00010 00011 This program is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program; if not, write to the Free Software 00018 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00019 00020 See http://creativecommons.org/licenses/GPL/2.0/ 00021 00022 MTU TTU Robotiklubi http://www.robotiklubi.ee robotiklubi@gmail.com 00023 Lauri Kirikal laurikirikal@gmail.com 00024 Mikk Leini mikk.leini@gmail.com 00025 00026 \**********************************************************************************************************************/ 00027 00028 #ifndef __AVR_CPP_ATMEGA64_IO_H__ 00029 #define __AVR_CPP_ATMEGA64_IO_H__ 00030 00031 #if defined(__DOXYGEN__) && !defined(__AVR_CPP_IO_H__) 00032 #include <avr/cpp/IO.h> 00033 #endif 00034 00035 #ifndef __AVR_CPP_IO_H__ 00036 #error "Include <avr/cpp/IO.h> instead of <avr/cpp/atmega64/IO.h>." 00037 #else 00038 00039 00040 /**********************************************************************************************************************\ 00041 00042 atmega64 registers, bits and ports declarations. 00043 This file is generated. Do not modify manually. 00044 00045 \**********************************************************************************************************************/ 00046 00047 // Registers 00048 namespace AVRCpp 00049 { 00050 __DECLARE_8BIT_REGISTER__(UCSR1C); 00051 __DECLARE_8BIT_REGISTER__(UDR1); 00052 __DECLARE_8BIT_REGISTER__(UCSR1A); 00053 __DECLARE_8BIT_REGISTER__(UCSR1B); 00054 __DECLARE_8BIT_REGISTER__(UBRR1L); 00055 __DECLARE_8BIT_REGISTER__(UBRR1H); 00056 __DECLARE_8BIT_REGISTER__(UCSR0C); 00057 __DECLARE_8BIT_REGISTER__(UBRR0H); 00058 __DECLARE_8BIT_REGISTER__(ADCSRB); 00059 __DECLARE_8BIT_REGISTER__(TCCR3C); 00060 __DECLARE_8BIT_REGISTER__(TCCR3A); 00061 __DECLARE_8BIT_REGISTER__(TCCR3B); 00062 __DECLARE_8BIT_REGISTER__(TCNT3H); 00063 __DECLARE_8BIT_REGISTER__(TCNT3L); 00064 __DECLARE_8BIT_REGISTER__(OCR3AH); 00065 __DECLARE_8BIT_REGISTER__(OCR3AL); 00066 __DECLARE_8BIT_REGISTER__(OCR3BH); 00067 __DECLARE_8BIT_REGISTER__(OCR3BL); 00068 __DECLARE_8BIT_REGISTER__(OCR3CH); 00069 __DECLARE_8BIT_REGISTER__(OCR3CL); 00070 __DECLARE_8BIT_REGISTER__(ICR3H); 00071 __DECLARE_8BIT_REGISTER__(ICR3L); 00072 __DECLARE_8BIT_REGISTER__(ETIMSK); 00073 __DECLARE_8BIT_REGISTER__(ETIFR); 00074 __DECLARE_8BIT_REGISTER__(TCCR1C); 00075 __DECLARE_8BIT_REGISTER__(OCR1CH); 00076 __DECLARE_8BIT_REGISTER__(OCR1CL); 00077 __DECLARE_8BIT_REGISTER__(TWCR); 00078 __DECLARE_8BIT_REGISTER__(TWDR); 00079 __DECLARE_8BIT_REGISTER__(TWAR); 00080 __DECLARE_8BIT_REGISTER__(TWSR); 00081 __DECLARE_8BIT_REGISTER__(TWBR); 00082 __DECLARE_8BIT_REGISTER__(OSCCAL); 00083 __DECLARE_8BIT_REGISTER__(XMCRA); 00084 __DECLARE_8BIT_REGISTER__(XMCRB); 00085 __DECLARE_8BIT_REGISTER__(EICRA); 00086 __DECLARE_8BIT_REGISTER__(SPMCSR); 00087 __DECLARE_8BIT_REGISTER__(PORTG); 00088 __DECLARE_8BIT_REGISTER__(DDRG); 00089 __DECLARE_8BIT_REGISTER__(PING); 00090 __DECLARE_8BIT_REGISTER__(PORTF); 00091 __DECLARE_8BIT_REGISTER__(DDRF); 00092 __DECLARE_8BIT_REGISTER__(SREG); 00093 __DECLARE_8BIT_REGISTER__(SPH); 00094 __DECLARE_8BIT_REGISTER__(SPL); 00095 __DECLARE_8BIT_REGISTER__(XDIV); 00096 __DECLARE_8BIT_REGISTER__(EICRB); 00097 __DECLARE_8BIT_REGISTER__(EIMSK); 00098 __DECLARE_8BIT_REGISTER__(EIFR); 00099 __DECLARE_8BIT_REGISTER__(TIMSK); 00100 __DECLARE_8BIT_REGISTER__(TIFR); 00101 __DECLARE_8BIT_REGISTER__(MCUCR); 00102 __DECLARE_8BIT_REGISTER__(MCUCSR); 00103 __DECLARE_8BIT_REGISTER__(TCCR0); 00104 __DECLARE_8BIT_REGISTER__(TCNT0); 00105 __DECLARE_8BIT_REGISTER__(OCR0); 00106 __DECLARE_8BIT_REGISTER__(ASSR); 00107 __DECLARE_8BIT_REGISTER__(TCCR1A); 00108 __DECLARE_8BIT_REGISTER__(TCCR1B); 00109 __DECLARE_8BIT_REGISTER__(TCNT1H); 00110 __DECLARE_8BIT_REGISTER__(TCNT1L); 00111 __DECLARE_8BIT_REGISTER__(OCR1AH); 00112 __DECLARE_8BIT_REGISTER__(OCR1AL); 00113 __DECLARE_8BIT_REGISTER__(OCR1BH); 00114 __DECLARE_8BIT_REGISTER__(OCR1BL); 00115 __DECLARE_8BIT_REGISTER__(ICR1H); 00116 __DECLARE_8BIT_REGISTER__(ICR1L); 00117 __DECLARE_8BIT_REGISTER__(TCCR2); 00118 __DECLARE_8BIT_REGISTER__(TCNT2); 00119 __DECLARE_8BIT_REGISTER__(OCR2); 00120 __DECLARE_8BIT_REGISTER__(OCDR); 00121 __DECLARE_8BIT_REGISTER__(WDTCR); 00122 __DECLARE_8BIT_REGISTER__(SFIOR); 00123 __DECLARE_8BIT_REGISTER__(EEARH); 00124 __DECLARE_8BIT_REGISTER__(EEARL); 00125 __DECLARE_8BIT_REGISTER__(EEDR); 00126 __DECLARE_8BIT_REGISTER__(EECR); 00127 __DECLARE_8BIT_REGISTER__(PORTA); 00128 __DECLARE_8BIT_REGISTER__(DDRA); 00129 __DECLARE_8BIT_REGISTER__(PINA); 00130 __DECLARE_8BIT_REGISTER__(PORTB); 00131 __DECLARE_8BIT_REGISTER__(DDRB); 00132 __DECLARE_8BIT_REGISTER__(PINB); 00133 __DECLARE_8BIT_REGISTER__(PORTC); 00134 __DECLARE_8BIT_REGISTER__(DDRC); 00135 __DECLARE_8BIT_REGISTER__(PINC); 00136 __DECLARE_8BIT_REGISTER__(PORTD); 00137 __DECLARE_8BIT_REGISTER__(DDRD); 00138 __DECLARE_8BIT_REGISTER__(PIND); 00139 __DECLARE_8BIT_REGISTER__(SPDR); 00140 __DECLARE_8BIT_REGISTER__(SPSR); 00141 __DECLARE_8BIT_REGISTER__(SPCR); 00142 __DECLARE_8BIT_REGISTER__(UDR0); 00143 __DECLARE_8BIT_REGISTER__(UCSR0A); 00144 __DECLARE_8BIT_REGISTER__(UCSR0B); 00145 __DECLARE_8BIT_REGISTER__(UBRR0L); 00146 __DECLARE_8BIT_REGISTER__(ACSR); 00147 __DECLARE_8BIT_REGISTER__(ADMUX); 00148 __DECLARE_8BIT_REGISTER__(ADCSRA); 00149 __DECLARE_8BIT_REGISTER__(ADCH); 00150 __DECLARE_8BIT_REGISTER__(ADCL); 00151 __DECLARE_8BIT_REGISTER__(PORTE); 00152 __DECLARE_8BIT_REGISTER__(DDRE); 00153 __DECLARE_8BIT_REGISTER__(PINE); 00154 __DECLARE_8BIT_REGISTER__(PINF); 00155 __DECLARE_16BIT_REGISTER__(TCNT3); 00156 __DECLARE_16BIT_REGISTER__(OCR3A); 00157 __DECLARE_16BIT_REGISTER__(OCR3B); 00158 __DECLARE_16BIT_REGISTER__(OCR3C); 00159 __DECLARE_16BIT_REGISTER__(ICR3); 00160 __DECLARE_16BIT_REGISTER__(OCR1C); 00161 __DECLARE_16BIT_REGISTER__(SP); 00162 __DECLARE_16BIT_REGISTER__(TCNT1); 00163 __DECLARE_16BIT_REGISTER__(OCR1A); 00164 __DECLARE_16BIT_REGISTER__(OCR1B); 00165 __DECLARE_16BIT_REGISTER__(ICR1); 00166 __DECLARE_16BIT_REGISTER__(ADC); 00167 00168 } // namespace AVRCpp 00169 00170 00171 // UCSR1C 00172 #define _UMSEL1 0x40 00173 #define _UPM11 0x20 00174 #define _UPM10 0x10 00175 #define _USBS1 0x8 00176 #define _UCSZ11 0x4 00177 #define _UCSZ10 0x2 00178 #define _UCPOL1 0x1 00179 00180 // UCSR1A 00181 #define _RXC1 0x80 00182 #define _TXC1 0x40 00183 #define _UDRE1 0x20 00184 #define _FE1 0x10 00185 #define _DOR1 0x8 00186 #define _UPE1 0x4 00187 #define _U2X1 0x2 00188 #define _MPCM1 0x1 00189 00190 // UCSR1B 00191 #define _RXCIE1 0x80 00192 #define _TXCIE1 0x40 00193 #define _UDRIE1 0x20 00194 #define _RXEN1 0x10 00195 #define _TXEN1 0x8 00196 #define _UCSZ12 0x4 00197 #define _RXB81 0x2 00198 #define _TXB81 0x1 00199 00200 // UCSR0C 00201 #define _UMSEL0 0x40 00202 #define _UPM01 0x20 00203 #define _UPM00 0x10 00204 #define _USBS0 0x8 00205 #define _UCSZ01 0x4 00206 #define _UCSZ00 0x2 00207 #define _UCPOL0 0x1 00208 00209 // ADCSRB 00210 #define _ADTS2 0x4 00211 #define _ADTS1 0x2 00212 #define _ADTS0 0x1 00213 00214 // TCCR3C 00215 #define _FOC3A 0x80 00216 #define _FOC3B 0x40 00217 #define _FOC3C 0x20 00218 00219 // TCCR3A 00220 #define _COM3A1 0x80 00221 #define _COM3A0 0x40 00222 #define _COM3B1 0x20 00223 #define _COM3B0 0x10 00224 #define _COM3C1 0x8 00225 #define _COM3C0 0x4 00226 #define _WGM31 0x2 00227 #define _WGM30 0x1 00228 00229 // TCCR3B 00230 #define _ICNC3 0x80 00231 #define _ICES3 0x40 00232 #define _WGM33 0x10 00233 #define _WGM32 0x8 00234 #define _CS32 0x4 00235 #define _CS31 0x2 00236 #define _CS30 0x1 00237 00238 // ETIMSK 00239 #define _TICIE3 0x20 00240 #define _OCIE3A 0x10 00241 #define _OCIE3B 0x8 00242 #define _TOIE3 0x4 00243 #define _OCIE3C 0x2 00244 #define _OCIE1C 0x1 00245 00246 // ETIFR 00247 #define _ICF3 0x20 00248 #define _OCF3A 0x10 00249 #define _OCF3B 0x8 00250 #define _TOV3 0x4 00251 #define _OCF3C 0x2 00252 #define _OCF1C 0x1 00253 00254 // TCCR1C 00255 #define _FOC1A 0x80 00256 #define _FOC1B 0x40 00257 #define _FOC1C 0x20 00258 00259 // TWCR 00260 #define _TWINT 0x80 00261 #define _TWEA 0x40 00262 #define _TWSTA 0x20 00263 #define _TWSTO 0x10 00264 #define _TWWC 0x8 00265 #define _TWEN 0x4 00266 #define _TWIE 0x1 00267 00268 // TWAR 00269 #define _TWA6 0x80 00270 #define _TWA5 0x40 00271 #define _TWA4 0x20 00272 #define _TWA3 0x10 00273 #define _TWA2 0x8 00274 #define _TWA1 0x4 00275 #define _TWA0 0x2 00276 #define _TWGCE 0x1 00277 00278 // TWSR 00279 #define _TWS7 0x80 00280 #define _TWS6 0x40 00281 #define _TWS5 0x20 00282 #define _TWS4 0x10 00283 #define _TWS3 0x8 00284 #define _TWPS1 0x2 00285 #define _TWPS0 0x1 00286 00287 // XMCRB 00288 #define _XMBK 0x80 00289 #define _XMM2 0x4 00290 #define _XMM1 0x2 00291 #define _XMM0 0x1 00292 00293 // EICRA 00294 #define _ISC31 0x80 00295 #define _ISC30 0x40 00296 #define _ISC21 0x20 00297 #define _ISC20 0x10 00298 #define _ISC11 0x8 00299 #define _ISC10 0x4 00300 #define _ISC01 0x2 00301 #define _ISC00 0x1 00302 00303 // SPMCSR 00304 #define _SPMIE 0x80 00305 #define _RWWSB 0x40 00306 #define _RWWSRE 0x10 00307 #define _BLBSET 0x8 00308 #define _PGWRT 0x4 00309 #define _PGERS 0x2 00310 #define _SPMEN 0x1 00311 00312 // PORTG 00313 #define _PG4 0x10 00314 #define _PG3 0x8 00315 #define _PG2 0x4 00316 #define _PG1 0x2 00317 #define _PG0 0x1 00318 00319 // DDRG 00320 #define _DDG4 0x10 00321 #define _DDG3 0x8 00322 #define _DDG2 0x4 00323 #define _DDG1 0x2 00324 #define _DDG0 0x1 00325 00326 // PING 00327 #define _PING4 0x10 00328 #define _PING3 0x8 00329 #define _PING2 0x4 00330 #define _PING1 0x2 00331 #define _PING0 0x1 00332 00333 // PORTF 00334 #define _PF7 0x80 00335 #define _PF6 0x40 00336 #define _PF5 0x20 00337 #define _PF4 0x10 00338 #define _PF3 0x8 00339 #define _PF2 0x4 00340 #define _PF1 0x2 00341 #define _PF0 0x1 00342 00343 // DDRF 00344 #define _DDF7 0x80 00345 #define _DDF6 0x40 00346 #define _DDF5 0x20 00347 #define _DDF4 0x10 00348 #define _DDF3 0x8 00349 #define _DDF2 0x4 00350 #define _DDF1 0x2 00351 #define _DDF0 0x1 00352 00353 // SREG 00354 #define _SREG_I 0x80 00355 #define _SREG_T 0x40 00356 #define _SREG_H 0x20 00357 #define _SREG_S 0x10 00358 #define _SREG_V 0x8 00359 #define _SREG_N 0x4 00360 #define _SREG_Z 0x2 00361 #define _SREG_C 0x1 00362 00363 // SPH 00364 #define _SP15 0x80 00365 #define _SP14 0x40 00366 #define _SP13 0x20 00367 #define _SP12 0x10 00368 #define _SP11 0x8 00369 #define _SP10 0x4 00370 #define _SP9 0x2 00371 #define _SP8 0x1 00372 00373 // SPL 00374 #define _SP7 0x80 00375 #define _SP6 0x40 00376 #define _SP5 0x20 00377 #define _SP4 0x10 00378 #define _SP3 0x8 00379 #define _SP2 0x4 00380 #define _SP1 0x2 00381 #define _SP0 0x1 00382 00383 // XDIV 00384 #define _XDIVEN 0x80 00385 #define _XDIV6 0x40 00386 #define _XDIV5 0x20 00387 #define _XDIV4 0x10 00388 #define _XDIV3 0x8 00389 #define _XDIV2 0x4 00390 #define _XDIV1 0x2 00391 #define _XDIV0 0x1 00392 00393 // EICRB 00394 #define _ISC71 0x80 00395 #define _ISC70 0x40 00396 #define _ISC61 0x20 00397 #define _ISC60 0x10 00398 #define _ISC51 0x8 00399 #define _ISC50 0x4 00400 #define _ISC41 0x2 00401 #define _ISC40 0x1 00402 00403 // EIMSK 00404 #define _INT7 0x80 00405 #define _INT6 0x40 00406 #define _INT5 0x20 00407 #define _INT4 0x10 00408 #define _INT3 0x8 00409 #define _INT2 0x4 00410 #define _INT1 0x2 00411 #define _INT0 0x1 00412 00413 // EIFR 00414 #define _INTF7 0x80 00415 #define _INTF6 0x40 00416 #define _INTF5 0x20 00417 #define _INTF4 0x10 00418 #define _INTF3 0x8 00419 #define _INTF2 0x4 00420 #define _INTF1 0x2 00421 #define _INTF0 0x1 00422 00423 // TIMSK 00424 #define _OCIE2 0x80 00425 #define _TOIE2 0x40 00426 #define _TICIE1 0x20 00427 #define _OCIE1A 0x10 00428 #define _OCIE1B 0x8 00429 #define _TOIE1 0x4 00430 #define _OCIE0 0x2 00431 #define _TOIE0 0x1 00432 00433 // TIFR 00434 #define _OCF2 0x80 00435 #define _TOV2 0x40 00436 #define _ICF1 0x20 00437 #define _OCF1A 0x10 00438 #define _OCF1B 0x8 00439 #define _TOV1 0x4 00440 #define _OCF0 0x2 00441 #define _TOV0 0x1 00442 00443 // MCUCR 00444 #define _SRE 0x80 00445 #define _SRW10 0x40 00446 #define _SE 0x20 00447 #define _SM1 0x10 00448 #define _SM0 0x8 00449 #define _SM2 0x4 00450 #define _IVSEL 0x2 00451 #define _IVCE 0x1 00452 00453 // MCUCSR 00454 #define _JTD 0x80 00455 #define _JTRF 0x10 00456 #define _WDRF 0x8 00457 #define _BORF 0x4 00458 #define _EXTRF 0x2 00459 #define _PORF 0x1 00460 00461 // TCCR0 00462 #define _FOC0 0x80 00463 #define _WGM00 0x40 00464 #define _COM01 0x20 00465 #define _COM00 0x10 00466 #define _WGM01 0x8 00467 #define _CS02 0x4 00468 #define _CS01 0x2 00469 #define _CS00 0x1 00470 00471 // ASSR 00472 #define _AS0 0x8 00473 #define _TCN0UB 0x4 00474 #define _OCR0UB 0x2 00475 #define _TCR0UB 0x1 00476 00477 // TCCR1A 00478 #define _COM1A1 0x80 00479 #define _COM1A0 0x40 00480 #define _COM1B1 0x20 00481 #define _COM1B0 0x10 00482 #define _COM1C1 0x8 00483 #define _COM1C0 0x4 00484 #define _WGM11 0x2 00485 #define _WGM10 0x1 00486 00487 // TCCR1B 00488 #define _ICNC1 0x80 00489 #define _ICES1 0x40 00490 #define _WGM13 0x10 00491 #define _WGM12 0x8 00492 #define _CS12 0x4 00493 #define _CS11 0x2 00494 #define _CS10 0x1 00495 00496 // TCCR2 00497 #define _FOC2 0x80 00498 #define _WGM20 0x40 00499 #define _COM21 0x20 00500 #define _COM20 0x10 00501 #define _WGM21 0x8 00502 #define _CS22 0x4 00503 #define _CS21 0x2 00504 #define _CS20 0x1 00505 00506 // OCDR 00507 #define _IDRD 0x80 00508 #define _OCDR7 0x80 00509 #define _OCDR6 0x40 00510 #define _OCDR5 0x20 00511 #define _OCDR4 0x10 00512 #define _OCDR3 0x8 00513 #define _OCDR2 0x4 00514 #define _OCDR1 0x2 00515 #define _OCDR0 0x1 00516 00517 // WDTCR 00518 #define _WDCE 0x10 00519 #define _WDE 0x8 00520 #define _WDP2 0x4 00521 #define _WDP1 0x2 00522 #define _WDP0 0x1 00523 00524 // SFIOR 00525 #define _TSM 0x80 00526 #define _ACME 0x8 00527 #define _PUD 0x4 00528 #define _PSR0 0x2 00529 #define _PSR321 0x1 00530 00531 // EECR 00532 #define _EERIE 0x8 00533 #define _EEMWE 0x4 00534 #define _EEWE 0x2 00535 #define _EERE 0x1 00536 00537 // PORTA 00538 #define _PA7 0x80 00539 #define _PA6 0x40 00540 #define _PA5 0x20 00541 #define _PA4 0x10 00542 #define _PA3 0x8 00543 #define _PA2 0x4 00544 #define _PA1 0x2 00545 #define _PA0 0x1 00546 00547 // DDRA 00548 #define _DDA7 0x80 00549 #define _DDA6 0x40 00550 #define _DDA5 0x20 00551 #define _DDA4 0x10 00552 #define _DDA3 0x8 00553 #define _DDA2 0x4 00554 #define _DDA1 0x2 00555 #define _DDA0 0x1 00556 00557 // PINA 00558 #define _PINA7 0x80 00559 #define _PINA6 0x40 00560 #define _PINA5 0x20 00561 #define _PINA4 0x10 00562 #define _PINA3 0x8 00563 #define _PINA2 0x4 00564 #define _PINA1 0x2 00565 #define _PINA0 0x1 00566 00567 // PORTB 00568 #define _PB7 0x80 00569 #define _PB6 0x40 00570 #define _PB5 0x20 00571 #define _PB4 0x10 00572 #define _PB3 0x8 00573 #define _PB2 0x4 00574 #define _PB1 0x2 00575 #define _PB0 0x1 00576 00577 // DDRB 00578 #define _DDB7 0x80 00579 #define _DDB6 0x40 00580 #define _DDB5 0x20 00581 #define _DDB4 0x10 00582 #define _DDB3 0x8 00583 #define _DDB2 0x4 00584 #define _DDB1 0x2 00585 #define _DDB0 0x1 00586 00587 // PINB 00588 #define _PINB7 0x80 00589 #define _PINB6 0x40 00590 #define _PINB5 0x20 00591 #define _PINB4 0x10 00592 #define _PINB3 0x8 00593 #define _PINB2 0x4 00594 #define _PINB1 0x2 00595 #define _PINB0 0x1 00596 00597 // PORTC 00598 #define _PC7 0x80 00599 #define _PC6 0x40 00600 #define _PC5 0x20 00601 #define _PC4 0x10 00602 #define _PC3 0x8 00603 #define _PC2 0x4 00604 #define _PC1 0x2 00605 #define _PC0 0x1 00606 00607 // DDRC 00608 #define _DDC7 0x80 00609 #define _DDC6 0x40 00610 #define _DDC5 0x20 00611 #define _DDC4 0x10 00612 #define _DDC3 0x8 00613 #define _DDC2 0x4 00614 #define _DDC1 0x2 00615 #define _DDC0 0x1 00616 00617 // PINC 00618 #define _PINC7 0x80 00619 #define _PINC6 0x40 00620 #define _PINC5 0x20 00621 #define _PINC4 0x10 00622 #define _PINC3 0x8 00623 #define _PINC2 0x4 00624 #define _PINC1 0x2 00625 #define _PINC0 0x1 00626 00627 // PORTD 00628 #define _PD7 0x80 00629 #define _PD6 0x40 00630 #define _PD5 0x20 00631 #define _PD4 0x10 00632 #define _PD3 0x8 00633 #define _PD2 0x4 00634 #define _PD1 0x2 00635 #define _PD0 0x1 00636 00637 // DDRD 00638 #define _DDD7 0x80 00639 #define _DDD6 0x40 00640 #define _DDD5 0x20 00641 #define _DDD4 0x10 00642 #define _DDD3 0x8 00643 #define _DDD2 0x4 00644 #define _DDD1 0x2 00645 #define _DDD0 0x1 00646 00647 // PIND 00648 #define _PIND7 0x80 00649 #define _PIND6 0x40 00650 #define _PIND5 0x20 00651 #define _PIND4 0x10 00652 #define _PIND3 0x8 00653 #define _PIND2 0x4 00654 #define _PIND1 0x2 00655 #define _PIND0 0x1 00656 00657 // SPSR 00658 #define _SPIF 0x80 00659 #define _WCOL 0x40 00660 #define _SPI2X 0x1 00661 00662 // SPCR 00663 #define _SPIE 0x80 00664 #define _SPE 0x40 00665 #define _DORD 0x20 00666 #define _MSTR 0x10 00667 #define _CPOL 0x8 00668 #define _CPHA 0x4 00669 #define _SPR1 0x2 00670 #define _SPR0 0x1 00671 00672 // UCSR0A 00673 #define _RXC0 0x80 00674 #define _TXC0 0x40 00675 #define _UDRE0 0x20 00676 #define _FE0 0x10 00677 #define _DOR0 0x8 00678 #define _UPE0 0x4 00679 #define _U2X0 0x2 00680 #define _MPCM0 0x1 00681 00682 // UCSR0B 00683 #define _RXCIE0 0x80 00684 #define _TXCIE0 0x40 00685 #define _UDRIE0 0x20 00686 #define _RXEN0 0x10 00687 #define _TXEN0 0x8 00688 #define _UCSZ02 0x4 00689 #define _RXB80 0x2 00690 #define _TXB80 0x1 00691 00692 // ACSR 00693 #define _ACD 0x80 00694 #define _ACBG 0x40 00695 #define _ACO 0x20 00696 #define _ACI 0x10 00697 #define _ACIE 0x8 00698 #define _ACIC 0x4 00699 #define _ACIS1 0x2 00700 #define _ACIS0 0x1 00701 00702 // ADMUX 00703 #define _REFS1 0x80 00704 #define _REFS0 0x40 00705 #define _ADLAR 0x20 00706 #define _MUX4 0x10 00707 #define _MUX3 0x8 00708 #define _MUX2 0x4 00709 #define _MUX1 0x2 00710 #define _MUX0 0x1 00711 00712 // ADCSRA 00713 #define _ADEN 0x80 00714 #define _ADSC 0x40 00715 #define _ADATE 0x20 00716 #define _ADIF 0x10 00717 #define _ADIE 0x8 00718 #define _ADPS2 0x4 00719 #define _ADPS1 0x2 00720 #define _ADPS0 0x1 00721 00722 // PORTE 00723 #define _PE7 0x80 00724 #define _PE6 0x40 00725 #define _PE5 0x20 00726 #define _PE4 0x10 00727 #define _PE3 0x8 00728 #define _PE2 0x4 00729 #define _PE1 0x2 00730 #define _PE0 0x1 00731 00732 // DDRE 00733 #define _DDE7 0x80 00734 #define _DDE6 0x40 00735 #define _DDE5 0x20 00736 #define _DDE4 0x10 00737 #define _DDE3 0x8 00738 #define _DDE2 0x4 00739 #define _DDE1 0x2 00740 #define _DDE0 0x1 00741 00742 // PINE 00743 #define _PINE7 0x80 00744 #define _PINE6 0x40 00745 #define _PINE5 0x20 00746 #define _PINE4 0x10 00747 #define _PINE3 0x8 00748 #define _PINE2 0x4 00749 #define _PINE1 0x2 00750 #define _PINE0 0x1 00751 00752 // PINF 00753 #define _PINF7 0x80 00754 #define _PINF6 0x40 00755 #define _PINF5 0x20 00756 #define _PINF4 0x10 00757 #define _PINF3 0x8 00758 #define _PINF2 0x4 00759 #define _PINF1 0x2 00760 #define _PINF0 0x1 00761 00762 00763 // General ports 00764 namespace AVRCpp 00765 { 00766 __DECLARE_PORT__(G); 00767 __DECLARE_PORT__(F); 00768 __DECLARE_PORT__(A); 00769 __DECLARE_PORT__(B); 00770 __DECLARE_PORT__(C); 00771 __DECLARE_PORT__(D); 00772 __DECLARE_PORT__(E); 00773 00774 } // namespace AVRCpp 00775 00776 00777 /**********************************************************************************************************************/ 00778 00779 #endif // ifndef __AVR_CPP_IO_H__ 00780 #endif // ifndef __AVR_CPP_ATMEGA64_IO_H__
1.5.2
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 MTÜ TTÜ Robotiklubi
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