00001 /**********************************************************************************************************************\ 00002 00003 C++ library for Atmel AVR microcontrollers 00004 Copyright (C) 2007 Lauri Kirikal, Mikk Leini, Rasmus Raag, MTU TTU Robotiklubi 00005 00006 This program is free software; you can redistribute it and/or 00007 modify it under the terms of the GNU General Public License 00008 as published by the Free Software Foundation; either version 2 00009 of the License, or (at your option) any later version. 00010 00011 This program is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program; if not, write to the Free Software 00018 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00019 00020 See http://creativecommons.org/licenses/GPL/2.0/ 00021 00022 MTU TTU Robotiklubi http://www.robotiklubi.ee robotiklubi@gmail.com 00023 Lauri Kirikal laurikirikal@gmail.com 00024 Mikk Leini mikk.leini@gmail.com 00025 00026 \**********************************************************************************************************************/ 00027 00028 #ifndef __AVR_CPP_ATMEGA128_IO_H__ 00029 #define __AVR_CPP_ATMEGA128_IO_H__ 00030 00031 #if defined(__DOXYGEN__) && !defined(__AVR_CPP_IO_H__) 00032 #include <avr/cpp/IO.h> 00033 #endif 00034 00035 #ifndef __AVR_CPP_IO_H__ 00036 #error "Include <avr/cpp/IO.h> instead of <avr/cpp/atmega128/IO.h>." 00037 #else 00038 00039 00040 /**********************************************************************************************************************\ 00041 00042 atmega128 registers, bits and ports declarations. 00043 This file is generated. Do not modify manually. 00044 00045 \**********************************************************************************************************************/ 00046 00047 // Registers 00048 namespace AVRCpp 00049 { 00050 __DECLARE_8BIT_REGISTER__(UCSR1C); 00051 __DECLARE_8BIT_REGISTER__(UDR1); 00052 __DECLARE_8BIT_REGISTER__(UCSR1A); 00053 __DECLARE_8BIT_REGISTER__(UCSR1B); 00054 __DECLARE_8BIT_REGISTER__(UBRR1L); 00055 __DECLARE_8BIT_REGISTER__(UBRR1H); 00056 __DECLARE_8BIT_REGISTER__(UCSR0C); 00057 __DECLARE_8BIT_REGISTER__(UBRR0H); 00058 __DECLARE_8BIT_REGISTER__(TCCR3C); 00059 __DECLARE_8BIT_REGISTER__(TCCR3A); 00060 __DECLARE_8BIT_REGISTER__(TCCR3B); 00061 __DECLARE_8BIT_REGISTER__(TCNT3H); 00062 __DECLARE_8BIT_REGISTER__(TCNT3L); 00063 __DECLARE_8BIT_REGISTER__(OCR3AH); 00064 __DECLARE_8BIT_REGISTER__(OCR3AL); 00065 __DECLARE_8BIT_REGISTER__(OCR3BH); 00066 __DECLARE_8BIT_REGISTER__(OCR3BL); 00067 __DECLARE_8BIT_REGISTER__(OCR3CH); 00068 __DECLARE_8BIT_REGISTER__(OCR3CL); 00069 __DECLARE_8BIT_REGISTER__(ICR3H); 00070 __DECLARE_8BIT_REGISTER__(ICR3L); 00071 __DECLARE_8BIT_REGISTER__(ETIMSK); 00072 __DECLARE_8BIT_REGISTER__(ETIFR); 00073 __DECLARE_8BIT_REGISTER__(TCCR1C); 00074 __DECLARE_8BIT_REGISTER__(OCR1CH); 00075 __DECLARE_8BIT_REGISTER__(OCR1CL); 00076 __DECLARE_8BIT_REGISTER__(TWCR); 00077 __DECLARE_8BIT_REGISTER__(TWDR); 00078 __DECLARE_8BIT_REGISTER__(TWAR); 00079 __DECLARE_8BIT_REGISTER__(TWSR); 00080 __DECLARE_8BIT_REGISTER__(TWBR); 00081 __DECLARE_8BIT_REGISTER__(OSCCAL); 00082 __DECLARE_8BIT_REGISTER__(XMCRA); 00083 __DECLARE_8BIT_REGISTER__(XMCRB); 00084 __DECLARE_8BIT_REGISTER__(EICRA); 00085 __DECLARE_8BIT_REGISTER__(SPMCSR); 00086 __DECLARE_8BIT_REGISTER__(PORTG); 00087 __DECLARE_8BIT_REGISTER__(DDRG); 00088 __DECLARE_8BIT_REGISTER__(PING); 00089 __DECLARE_8BIT_REGISTER__(PORTF); 00090 __DECLARE_8BIT_REGISTER__(DDRF); 00091 __DECLARE_8BIT_REGISTER__(SREG); 00092 __DECLARE_8BIT_REGISTER__(SPH); 00093 __DECLARE_8BIT_REGISTER__(SPL); 00094 __DECLARE_8BIT_REGISTER__(XDIV); 00095 __DECLARE_8BIT_REGISTER__(RAMPZ); 00096 __DECLARE_8BIT_REGISTER__(EICRB); 00097 __DECLARE_8BIT_REGISTER__(EIMSK); 00098 __DECLARE_8BIT_REGISTER__(EIFR); 00099 __DECLARE_8BIT_REGISTER__(TIMSK); 00100 __DECLARE_8BIT_REGISTER__(TIFR); 00101 __DECLARE_8BIT_REGISTER__(MCUCR); 00102 __DECLARE_8BIT_REGISTER__(MCUCSR); 00103 __DECLARE_8BIT_REGISTER__(TCCR0); 00104 __DECLARE_8BIT_REGISTER__(TCNT0); 00105 __DECLARE_8BIT_REGISTER__(OCR0); 00106 __DECLARE_8BIT_REGISTER__(ASSR); 00107 __DECLARE_8BIT_REGISTER__(TCCR1A); 00108 __DECLARE_8BIT_REGISTER__(TCCR1B); 00109 __DECLARE_8BIT_REGISTER__(TCNT1H); 00110 __DECLARE_8BIT_REGISTER__(TCNT1L); 00111 __DECLARE_8BIT_REGISTER__(OCR1AH); 00112 __DECLARE_8BIT_REGISTER__(OCR1AL); 00113 __DECLARE_8BIT_REGISTER__(OCR1BH); 00114 __DECLARE_8BIT_REGISTER__(OCR1BL); 00115 __DECLARE_8BIT_REGISTER__(ICR1H); 00116 __DECLARE_8BIT_REGISTER__(ICR1L); 00117 __DECLARE_8BIT_REGISTER__(TCCR2); 00118 __DECLARE_8BIT_REGISTER__(TCNT2); 00119 __DECLARE_8BIT_REGISTER__(OCR2); 00120 __DECLARE_8BIT_REGISTER__(OCDR); 00121 __DECLARE_8BIT_REGISTER__(WDTCR); 00122 __DECLARE_8BIT_REGISTER__(SFIOR); 00123 __DECLARE_8BIT_REGISTER__(EEARH); 00124 __DECLARE_8BIT_REGISTER__(EEARL); 00125 __DECLARE_8BIT_REGISTER__(EEDR); 00126 __DECLARE_8BIT_REGISTER__(EECR); 00127 __DECLARE_8BIT_REGISTER__(PORTA); 00128 __DECLARE_8BIT_REGISTER__(DDRA); 00129 __DECLARE_8BIT_REGISTER__(PINA); 00130 __DECLARE_8BIT_REGISTER__(PORTB); 00131 __DECLARE_8BIT_REGISTER__(DDRB); 00132 __DECLARE_8BIT_REGISTER__(PINB); 00133 __DECLARE_8BIT_REGISTER__(PORTC); 00134 __DECLARE_8BIT_REGISTER__(DDRC); 00135 __DECLARE_8BIT_REGISTER__(PINC); 00136 __DECLARE_8BIT_REGISTER__(PORTD); 00137 __DECLARE_8BIT_REGISTER__(DDRD); 00138 __DECLARE_8BIT_REGISTER__(PIND); 00139 __DECLARE_8BIT_REGISTER__(SPDR); 00140 __DECLARE_8BIT_REGISTER__(SPSR); 00141 __DECLARE_8BIT_REGISTER__(SPCR); 00142 __DECLARE_8BIT_REGISTER__(UDR0); 00143 __DECLARE_8BIT_REGISTER__(UCSR0A); 00144 __DECLARE_8BIT_REGISTER__(UCSR0B); 00145 __DECLARE_8BIT_REGISTER__(UBRR0L); 00146 __DECLARE_8BIT_REGISTER__(ACSR); 00147 __DECLARE_8BIT_REGISTER__(ADMUX); 00148 __DECLARE_8BIT_REGISTER__(ADCSRA); 00149 __DECLARE_8BIT_REGISTER__(ADCH); 00150 __DECLARE_8BIT_REGISTER__(ADCL); 00151 __DECLARE_8BIT_REGISTER__(PORTE); 00152 __DECLARE_8BIT_REGISTER__(DDRE); 00153 __DECLARE_8BIT_REGISTER__(PINE); 00154 __DECLARE_8BIT_REGISTER__(PINF); 00155 __DECLARE_16BIT_REGISTER__(TCNT3); 00156 __DECLARE_16BIT_REGISTER__(OCR3A); 00157 __DECLARE_16BIT_REGISTER__(OCR3B); 00158 __DECLARE_16BIT_REGISTER__(OCR3C); 00159 __DECLARE_16BIT_REGISTER__(ICR3); 00160 __DECLARE_16BIT_REGISTER__(OCR1C); 00161 __DECLARE_16BIT_REGISTER__(SP); 00162 __DECLARE_16BIT_REGISTER__(TCNT1); 00163 __DECLARE_16BIT_REGISTER__(OCR1A); 00164 __DECLARE_16BIT_REGISTER__(OCR1B); 00165 __DECLARE_16BIT_REGISTER__(ICR1); 00166 __DECLARE_16BIT_REGISTER__(ADC); 00167 00168 } // namespace AVRCpp 00169 00170 00171 // UCSR1C 00172 #define _UMSEL1 0x40 00173 #define _UPM11 0x20 00174 #define _UPM10 0x10 00175 #define _USBS1 0x8 00176 #define _UCSZ11 0x4 00177 #define _UCSZ10 0x2 00178 #define _UCPOL1 0x1 00179 00180 // UCSR1A 00181 #define _RXC1 0x80 00182 #define _TXC1 0x40 00183 #define _UDRE1 0x20 00184 #define _FE1 0x10 00185 #define _DOR1 0x8 00186 #define _UPE1 0x4 00187 #define _U2X1 0x2 00188 #define _MPCM1 0x1 00189 00190 // UCSR1B 00191 #define _RXCIE1 0x80 00192 #define _TXCIE1 0x40 00193 #define _UDRIE1 0x20 00194 #define _RXEN1 0x10 00195 #define _TXEN1 0x8 00196 #define _UCSZ12 0x4 00197 #define _RXB81 0x2 00198 #define _TXB81 0x1 00199 00200 // UCSR0C 00201 #define _UMSEL0 0x40 00202 #define _UPM01 0x20 00203 #define _UPM00 0x10 00204 #define _USBS0 0x8 00205 #define _UCSZ01 0x4 00206 #define _UCSZ00 0x2 00207 #define _UCPOL0 0x1 00208 00209 // TCCR3C 00210 #define _FOC3A 0x80 00211 #define _FOC3B 0x40 00212 #define _FOC3C 0x20 00213 00214 // TCCR3A 00215 #define _COM3A1 0x80 00216 #define _COM3A0 0x40 00217 #define _COM3B1 0x20 00218 #define _COM3B0 0x10 00219 #define _COM3C1 0x8 00220 #define _COM3C0 0x4 00221 #define _WGM31 0x2 00222 #define _WGM30 0x1 00223 00224 // TCCR3B 00225 #define _ICNC3 0x80 00226 #define _ICES3 0x40 00227 #define _WGM33 0x10 00228 #define _WGM32 0x8 00229 #define _CS32 0x4 00230 #define _CS31 0x2 00231 #define _CS30 0x1 00232 00233 // ETIMSK 00234 #define _TICIE3 0x20 00235 #define _OCIE3A 0x10 00236 #define _OCIE3B 0x8 00237 #define _TOIE3 0x4 00238 #define _OCIE3C 0x2 00239 #define _OCIE1C 0x1 00240 00241 // ETIFR 00242 #define _ICF3 0x20 00243 #define _OCF3A 0x10 00244 #define _OCF3B 0x8 00245 #define _TOV3 0x4 00246 #define _OCF3C 0x2 00247 #define _OCF1C 0x1 00248 00249 // TCCR1C 00250 #define _FOC1A 0x80 00251 #define _FOC1B 0x40 00252 #define _FOC1C 0x20 00253 00254 // TWCR 00255 #define _TWINT 0x80 00256 #define _TWEA 0x40 00257 #define _TWSTA 0x20 00258 #define _TWSTO 0x10 00259 #define _TWWC 0x8 00260 #define _TWEN 0x4 00261 #define _TWIE 0x1 00262 00263 // TWAR 00264 #define _TWA6 0x80 00265 #define _TWA5 0x40 00266 #define _TWA4 0x20 00267 #define _TWA3 0x10 00268 #define _TWA2 0x8 00269 #define _TWA1 0x4 00270 #define _TWA0 0x2 00271 #define _TWGCE 0x1 00272 00273 // TWSR 00274 #define _TWS7 0x80 00275 #define _TWS6 0x40 00276 #define _TWS5 0x20 00277 #define _TWS4 0x10 00278 #define _TWS3 0x8 00279 #define _TWPS1 0x2 00280 #define _TWPS0 0x1 00281 00282 // XMCRB 00283 #define _XMBK 0x80 00284 #define _XMM2 0x4 00285 #define _XMM1 0x2 00286 #define _XMM0 0x1 00287 00288 // EICRA 00289 #define _ISC31 0x80 00290 #define _ISC30 0x40 00291 #define _ISC21 0x20 00292 #define _ISC20 0x10 00293 #define _ISC11 0x8 00294 #define _ISC10 0x4 00295 #define _ISC01 0x2 00296 #define _ISC00 0x1 00297 00298 // SPMCSR 00299 #define _SPMIE 0x80 00300 #define _RWWSB 0x40 00301 #define _RWWSRE 0x10 00302 #define _BLBSET 0x8 00303 #define _PGWRT 0x4 00304 #define _PGERS 0x2 00305 #define _SPMEN 0x1 00306 00307 // PORTG 00308 #define _PG4 0x10 00309 #define _PG3 0x8 00310 #define _PG2 0x4 00311 #define _PG1 0x2 00312 #define _PG0 0x1 00313 00314 // DDRG 00315 #define _DDG4 0x10 00316 #define _DDG3 0x8 00317 #define _DDG2 0x4 00318 #define _DDG1 0x2 00319 #define _DDG0 0x1 00320 00321 // PING 00322 #define _PING4 0x10 00323 #define _PING3 0x8 00324 #define _PING2 0x4 00325 #define _PING1 0x2 00326 #define _PING0 0x1 00327 00328 // PORTF 00329 #define _PF7 0x80 00330 #define _PF6 0x40 00331 #define _PF5 0x20 00332 #define _PF4 0x10 00333 #define _PF3 0x8 00334 #define _PF2 0x4 00335 #define _PF1 0x2 00336 #define _PF0 0x1 00337 00338 // DDRF 00339 #define _DDF7 0x80 00340 #define _DDF6 0x40 00341 #define _DDF5 0x20 00342 #define _DDF4 0x10 00343 #define _DDF3 0x8 00344 #define _DDF2 0x4 00345 #define _DDF1 0x2 00346 #define _DDF0 0x1 00347 00348 // SREG 00349 #define _SREG_I 0x80 00350 #define _SREG_T 0x40 00351 #define _SREG_H 0x20 00352 #define _SREG_S 0x10 00353 #define _SREG_V 0x8 00354 #define _SREG_N 0x4 00355 #define _SREG_Z 0x2 00356 #define _SREG_C 0x1 00357 00358 // SPH 00359 #define _SP15 0x80 00360 #define _SP14 0x40 00361 #define _SP13 0x20 00362 #define _SP12 0x10 00363 #define _SP11 0x8 00364 #define _SP10 0x4 00365 #define _SP9 0x2 00366 #define _SP8 0x1 00367 00368 // SPL 00369 #define _SP7 0x80 00370 #define _SP6 0x40 00371 #define _SP5 0x20 00372 #define _SP4 0x10 00373 #define _SP3 0x8 00374 #define _SP2 0x4 00375 #define _SP1 0x2 00376 #define _SP0 0x1 00377 00378 // XDIV 00379 #define _XDIVEN 0x80 00380 #define _XDIV6 0x40 00381 #define _XDIV5 0x20 00382 #define _XDIV4 0x10 00383 #define _XDIV3 0x8 00384 #define _XDIV2 0x4 00385 #define _XDIV1 0x2 00386 #define _XDIV0 0x1 00387 00388 // RAMPZ 00389 #define _RAMPZ0 0x1 00390 00391 // EICRB 00392 #define _ISC71 0x80 00393 #define _ISC70 0x40 00394 #define _ISC61 0x20 00395 #define _ISC60 0x10 00396 #define _ISC51 0x8 00397 #define _ISC50 0x4 00398 #define _ISC41 0x2 00399 #define _ISC40 0x1 00400 00401 // EIMSK 00402 #define _INT7 0x80 00403 #define _INT6 0x40 00404 #define _INT5 0x20 00405 #define _INT4 0x10 00406 #define _INT3 0x8 00407 #define _INT2 0x4 00408 #define _INT1 0x2 00409 #define _INT0 0x1 00410 00411 // EIFR 00412 #define _INTF7 0x80 00413 #define _INTF6 0x40 00414 #define _INTF5 0x20 00415 #define _INTF4 0x10 00416 #define _INTF3 0x8 00417 #define _INTF2 0x4 00418 #define _INTF1 0x2 00419 #define _INTF0 0x1 00420 00421 // TIMSK 00422 #define _OCIE2 0x80 00423 #define _TOIE2 0x40 00424 #define _TICIE1 0x20 00425 #define _OCIE1A 0x10 00426 #define _OCIE1B 0x8 00427 #define _TOIE1 0x4 00428 #define _OCIE0 0x2 00429 #define _TOIE0 0x1 00430 00431 // TIFR 00432 #define _OCF2 0x80 00433 #define _TOV2 0x40 00434 #define _ICF1 0x20 00435 #define _OCF1A 0x10 00436 #define _OCF1B 0x8 00437 #define _TOV1 0x4 00438 #define _OCF0 0x2 00439 #define _TOV0 0x1 00440 00441 // MCUCR 00442 #define _SRE 0x80 00443 #define _SRW10 0x40 00444 #define _SE 0x20 00445 #define _SM1 0x10 00446 #define _SM0 0x8 00447 #define _SM2 0x4 00448 #define _IVSEL 0x2 00449 #define _IVCE 0x1 00450 00451 // MCUCSR 00452 #define _JTD 0x80 00453 #define _JTRF 0x10 00454 #define _WDRF 0x8 00455 #define _BORF 0x4 00456 #define _EXTRF 0x2 00457 #define _PORF 0x1 00458 00459 // TCCR0 00460 #define _FOC0 0x80 00461 #define _WGM00 0x40 00462 #define _COM01 0x20 00463 #define _COM00 0x10 00464 #define _WGM01 0x8 00465 #define _CS02 0x4 00466 #define _CS01 0x2 00467 #define _CS00 0x1 00468 00469 // ASSR 00470 #define _AS0 0x8 00471 #define _TCN0UB 0x4 00472 #define _OCR0UB 0x2 00473 #define _TCR0UB 0x1 00474 00475 // TCCR1A 00476 #define _COM1A1 0x80 00477 #define _COM1A0 0x40 00478 #define _COM1B1 0x20 00479 #define _COM1B0 0x10 00480 #define _COM1C1 0x8 00481 #define _COM1C0 0x4 00482 #define _WGM11 0x2 00483 #define _WGM10 0x1 00484 00485 // TCCR1B 00486 #define _ICNC1 0x80 00487 #define _ICES1 0x40 00488 #define _WGM13 0x10 00489 #define _WGM12 0x8 00490 #define _CS12 0x4 00491 #define _CS11 0x2 00492 #define _CS10 0x1 00493 00494 // TCCR2 00495 #define _FOC2 0x80 00496 #define _WGM20 0x40 00497 #define _COM21 0x20 00498 #define _COM20 0x10 00499 #define _WGM21 0x8 00500 #define _CS22 0x4 00501 #define _CS21 0x2 00502 #define _CS20 0x1 00503 00504 // OCDR 00505 #define _IDRD 0x80 00506 #define _OCDR7 0x80 00507 #define _OCDR6 0x40 00508 #define _OCDR5 0x20 00509 #define _OCDR4 0x10 00510 #define _OCDR3 0x8 00511 #define _OCDR2 0x4 00512 #define _OCDR1 0x2 00513 #define _OCDR0 0x1 00514 00515 // WDTCR 00516 #define _WDCE 0x10 00517 #define _WDE 0x8 00518 #define _WDP2 0x4 00519 #define _WDP1 0x2 00520 #define _WDP0 0x1 00521 00522 // SFIOR 00523 #define _TSM 0x80 00524 #define _ACME 0x8 00525 #define _PUD 0x4 00526 #define _PSR0 0x2 00527 #define _PSR321 0x1 00528 00529 // EECR 00530 #define _EERIE 0x8 00531 #define _EEMWE 0x4 00532 #define _EEWE 0x2 00533 #define _EERE 0x1 00534 00535 // PORTA 00536 #define _PA7 0x80 00537 #define _PA6 0x40 00538 #define _PA5 0x20 00539 #define _PA4 0x10 00540 #define _PA3 0x8 00541 #define _PA2 0x4 00542 #define _PA1 0x2 00543 #define _PA0 0x1 00544 00545 // DDRA 00546 #define _DDA7 0x80 00547 #define _DDA6 0x40 00548 #define _DDA5 0x20 00549 #define _DDA4 0x10 00550 #define _DDA3 0x8 00551 #define _DDA2 0x4 00552 #define _DDA1 0x2 00553 #define _DDA0 0x1 00554 00555 // PINA 00556 #define _PINA7 0x80 00557 #define _PINA6 0x40 00558 #define _PINA5 0x20 00559 #define _PINA4 0x10 00560 #define _PINA3 0x8 00561 #define _PINA2 0x4 00562 #define _PINA1 0x2 00563 #define _PINA0 0x1 00564 00565 // PORTB 00566 #define _PB7 0x80 00567 #define _PB6 0x40 00568 #define _PB5 0x20 00569 #define _PB4 0x10 00570 #define _PB3 0x8 00571 #define _PB2 0x4 00572 #define _PB1 0x2 00573 #define _PB0 0x1 00574 00575 // DDRB 00576 #define _DDB7 0x80 00577 #define _DDB6 0x40 00578 #define _DDB5 0x20 00579 #define _DDB4 0x10 00580 #define _DDB3 0x8 00581 #define _DDB2 0x4 00582 #define _DDB1 0x2 00583 #define _DDB0 0x1 00584 00585 // PINB 00586 #define _PINB7 0x80 00587 #define _PINB6 0x40 00588 #define _PINB5 0x20 00589 #define _PINB4 0x10 00590 #define _PINB3 0x8 00591 #define _PINB2 0x4 00592 #define _PINB1 0x2 00593 #define _PINB0 0x1 00594 00595 // PORTC 00596 #define _PC7 0x80 00597 #define _PC6 0x40 00598 #define _PC5 0x20 00599 #define _PC4 0x10 00600 #define _PC3 0x8 00601 #define _PC2 0x4 00602 #define _PC1 0x2 00603 #define _PC0 0x1 00604 00605 // DDRC 00606 #define _DDC7 0x80 00607 #define _DDC6 0x40 00608 #define _DDC5 0x20 00609 #define _DDC4 0x10 00610 #define _DDC3 0x8 00611 #define _DDC2 0x4 00612 #define _DDC1 0x2 00613 #define _DDC0 0x1 00614 00615 // PINC 00616 #define _PINC7 0x80 00617 #define _PINC6 0x40 00618 #define _PINC5 0x20 00619 #define _PINC4 0x10 00620 #define _PINC3 0x8 00621 #define _PINC2 0x4 00622 #define _PINC1 0x2 00623 #define _PINC0 0x1 00624 00625 // PORTD 00626 #define _PD7 0x80 00627 #define _PD6 0x40 00628 #define _PD5 0x20 00629 #define _PD4 0x10 00630 #define _PD3 0x8 00631 #define _PD2 0x4 00632 #define _PD1 0x2 00633 #define _PD0 0x1 00634 00635 // DDRD 00636 #define _DDD7 0x80 00637 #define _DDD6 0x40 00638 #define _DDD5 0x20 00639 #define _DDD4 0x10 00640 #define _DDD3 0x8 00641 #define _DDD2 0x4 00642 #define _DDD1 0x2 00643 #define _DDD0 0x1 00644 00645 // PIND 00646 #define _PIND7 0x80 00647 #define _PIND6 0x40 00648 #define _PIND5 0x20 00649 #define _PIND4 0x10 00650 #define _PIND3 0x8 00651 #define _PIND2 0x4 00652 #define _PIND1 0x2 00653 #define _PIND0 0x1 00654 00655 // SPSR 00656 #define _SPIF 0x80 00657 #define _WCOL 0x40 00658 #define _SPI2X 0x1 00659 00660 // SPCR 00661 #define _SPIE 0x80 00662 #define _SPE 0x40 00663 #define _DORD 0x20 00664 #define _MSTR 0x10 00665 #define _CPOL 0x8 00666 #define _CPHA 0x4 00667 #define _SPR1 0x2 00668 #define _SPR0 0x1 00669 00670 // UCSR0A 00671 #define _RXC0 0x80 00672 #define _TXC0 0x40 00673 #define _UDRE0 0x20 00674 #define _FE0 0x10 00675 #define _DOR0 0x8 00676 #define _UPE0 0x4 00677 #define _U2X0 0x2 00678 #define _MPCM0 0x1 00679 00680 // UCSR0B 00681 #define _RXCIE0 0x80 00682 #define _TXCIE0 0x40 00683 #define _UDRIE0 0x20 00684 #define _RXEN0 0x10 00685 #define _TXEN0 0x8 00686 #define _UCSZ02 0x4 00687 #define _RXB80 0x2 00688 #define _TXB80 0x1 00689 00690 // ACSR 00691 #define _ACD 0x80 00692 #define _ACBG 0x40 00693 #define _ACO 0x20 00694 #define _ACI 0x10 00695 #define _ACIE 0x8 00696 #define _ACIC 0x4 00697 #define _ACIS1 0x2 00698 #define _ACIS0 0x1 00699 00700 // ADMUX 00701 #define _REFS1 0x80 00702 #define _REFS0 0x40 00703 #define _ADLAR 0x20 00704 #define _MUX4 0x10 00705 #define _MUX3 0x8 00706 #define _MUX2 0x4 00707 #define _MUX1 0x2 00708 #define _MUX0 0x1 00709 00710 // ADCSRA 00711 #define _ADEN 0x80 00712 #define _ADSC 0x40 00713 #define _ADFR 0x20 00714 #define _ADIF 0x10 00715 #define _ADIE 0x8 00716 #define _ADPS2 0x4 00717 #define _ADPS1 0x2 00718 #define _ADPS0 0x1 00719 00720 // PORTE 00721 #define _PE7 0x80 00722 #define _PE6 0x40 00723 #define _PE5 0x20 00724 #define _PE4 0x10 00725 #define _PE3 0x8 00726 #define _PE2 0x4 00727 #define _PE1 0x2 00728 #define _PE0 0x1 00729 00730 // DDRE 00731 #define _DDE7 0x80 00732 #define _DDE6 0x40 00733 #define _DDE5 0x20 00734 #define _DDE4 0x10 00735 #define _DDE3 0x8 00736 #define _DDE2 0x4 00737 #define _DDE1 0x2 00738 #define _DDE0 0x1 00739 00740 // PINE 00741 #define _PINE7 0x80 00742 #define _PINE6 0x40 00743 #define _PINE5 0x20 00744 #define _PINE4 0x10 00745 #define _PINE3 0x8 00746 #define _PINE2 0x4 00747 #define _PINE1 0x2 00748 #define _PINE0 0x1 00749 00750 // PINF 00751 #define _PINF7 0x80 00752 #define _PINF6 0x40 00753 #define _PINF5 0x20 00754 #define _PINF4 0x10 00755 #define _PINF3 0x8 00756 #define _PINF2 0x4 00757 #define _PINF1 0x2 00758 #define _PINF0 0x1 00759 00760 00761 // General ports 00762 namespace AVRCpp 00763 { 00764 __DECLARE_PORT__(G); 00765 __DECLARE_PORT__(F); 00766 __DECLARE_PORT__(A); 00767 __DECLARE_PORT__(B); 00768 __DECLARE_PORT__(C); 00769 __DECLARE_PORT__(D); 00770 __DECLARE_PORT__(E); 00771 00772 } // namespace AVRCpp 00773 00774 00775 /**********************************************************************************************************************/ 00776 00777 #endif // ifndef __AVR_CPP_IO_H__ 00778 #endif // ifndef __AVR_CPP_ATMEGA128_IO_H__
1.5.2
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 MTÜ TTÜ Robotiklubi
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