00001 /**********************************************************************************************************************\ 00002 00003 C++ library for Atmel AVR microcontrollers 00004 Copyright (C) 2007 Lauri Kirikal, Mikk Leini, Rasmus Raag, MTU TTU Robotiklubi 00005 00006 This program is free software; you can redistribute it and/or 00007 modify it under the terms of the GNU General Public License 00008 as published by the Free Software Foundation; either version 2 00009 of the License, or (at your option) any later version. 00010 00011 This program is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program; if not, write to the Free Software 00018 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00019 00020 See http://creativecommons.org/licenses/GPL/2.0/ 00021 00022 MTU TTU Robotiklubi http://www.robotiklubi.ee robotiklubi@gmail.com 00023 Lauri Kirikal laurikirikal@gmail.com 00024 Mikk Leini mikk.leini@gmail.com 00025 00026 \**********************************************************************************************************************/ 00027 00028 #ifndef __AVR_CPP_ATMEGA644_IO_H__ 00029 #define __AVR_CPP_ATMEGA644_IO_H__ 00030 00031 #if defined(__DOXYGEN__) && !defined(__AVR_CPP_IO_H__) 00032 #include <avr/cpp/IO.h> 00033 #endif 00034 00035 #ifndef __AVR_CPP_IO_H__ 00036 #error "Include <avr/cpp/IO.h> instead of <avr/cpp/atmega644/IO.h>." 00037 #else 00038 00039 00040 /**********************************************************************************************************************\ 00041 00042 atmega644 registers, bits and ports declarations. 00043 This file is generated. Do not modify manually. 00044 00045 \**********************************************************************************************************************/ 00046 00047 // Registers 00048 namespace AVRCpp 00049 { 00050 __DECLARE_8BIT_REGISTER__(PINA); 00051 __DECLARE_8BIT_REGISTER__(UDR0); 00052 __DECLARE_8BIT_REGISTER__(UBRR0H); 00053 __DECLARE_8BIT_REGISTER__(UBRR0L); 00054 __DECLARE_8BIT_REGISTER__(UCSR0C); 00055 __DECLARE_8BIT_REGISTER__(UCSR0B); 00056 __DECLARE_8BIT_REGISTER__(UCSR0A); 00057 __DECLARE_8BIT_REGISTER__(TWAMR); 00058 __DECLARE_8BIT_REGISTER__(TWCR); 00059 __DECLARE_8BIT_REGISTER__(TWDR); 00060 __DECLARE_8BIT_REGISTER__(TWAR); 00061 __DECLARE_8BIT_REGISTER__(TWSR); 00062 __DECLARE_8BIT_REGISTER__(TWBR); 00063 __DECLARE_8BIT_REGISTER__(ASSR); 00064 __DECLARE_8BIT_REGISTER__(OCR2B); 00065 __DECLARE_8BIT_REGISTER__(OCR2A); 00066 __DECLARE_8BIT_REGISTER__(TCNT2); 00067 __DECLARE_8BIT_REGISTER__(TCCR2B); 00068 __DECLARE_8BIT_REGISTER__(TCCR2A); 00069 __DECLARE_8BIT_REGISTER__(OCR1BH); 00070 __DECLARE_8BIT_REGISTER__(OCR1BL); 00071 __DECLARE_8BIT_REGISTER__(OCR1AH); 00072 __DECLARE_8BIT_REGISTER__(OCR1AL); 00073 __DECLARE_8BIT_REGISTER__(ICR1H); 00074 __DECLARE_8BIT_REGISTER__(ICR1L); 00075 __DECLARE_8BIT_REGISTER__(TCNT1H); 00076 __DECLARE_8BIT_REGISTER__(TCNT1L); 00077 __DECLARE_8BIT_REGISTER__(TCCR1C); 00078 __DECLARE_8BIT_REGISTER__(TCCR1B); 00079 __DECLARE_8BIT_REGISTER__(TCCR1A); 00080 __DECLARE_8BIT_REGISTER__(DIDR1); 00081 __DECLARE_8BIT_REGISTER__(DIDR0); 00082 __DECLARE_8BIT_REGISTER__(ADMUX); 00083 __DECLARE_8BIT_REGISTER__(ADCSRB); 00084 __DECLARE_8BIT_REGISTER__(ADCSRA); 00085 __DECLARE_8BIT_REGISTER__(ADCH); 00086 __DECLARE_8BIT_REGISTER__(ADCL); 00087 __DECLARE_8BIT_REGISTER__(PCMSK3); 00088 __DECLARE_8BIT_REGISTER__(TIMSK2); 00089 __DECLARE_8BIT_REGISTER__(TIMSK1); 00090 __DECLARE_8BIT_REGISTER__(TIMSK0); 00091 __DECLARE_8BIT_REGISTER__(PCMSK2); 00092 __DECLARE_8BIT_REGISTER__(PCMSK1); 00093 __DECLARE_8BIT_REGISTER__(PCMSK0); 00094 __DECLARE_8BIT_REGISTER__(EICRA); 00095 __DECLARE_8BIT_REGISTER__(PCICR); 00096 __DECLARE_8BIT_REGISTER__(OSCCAL); 00097 __DECLARE_8BIT_REGISTER__(PRR); 00098 __DECLARE_8BIT_REGISTER__(CLKPR); 00099 __DECLARE_8BIT_REGISTER__(WDTCSR); 00100 __DECLARE_8BIT_REGISTER__(SREG); 00101 __DECLARE_8BIT_REGISTER__(SPH); 00102 __DECLARE_8BIT_REGISTER__(SPL); 00103 __DECLARE_8BIT_REGISTER__(SPMCSR); 00104 __DECLARE_8BIT_REGISTER__(MCUCR); 00105 __DECLARE_8BIT_REGISTER__(MCUSR); 00106 __DECLARE_8BIT_REGISTER__(SMCR); 00107 __DECLARE_8BIT_REGISTER__(OCDR); 00108 __DECLARE_8BIT_REGISTER__(ACSR); 00109 __DECLARE_8BIT_REGISTER__(SPDR); 00110 __DECLARE_8BIT_REGISTER__(SPSR); 00111 __DECLARE_8BIT_REGISTER__(SPCR); 00112 __DECLARE_8BIT_REGISTER__(GPIOR2); 00113 __DECLARE_8BIT_REGISTER__(GPIOR1); 00114 __DECLARE_8BIT_REGISTER__(OCR0B); 00115 __DECLARE_8BIT_REGISTER__(OCR0A); 00116 __DECLARE_8BIT_REGISTER__(TCNT0); 00117 __DECLARE_8BIT_REGISTER__(TCCR0B); 00118 __DECLARE_8BIT_REGISTER__(TCCR0A); 00119 __DECLARE_8BIT_REGISTER__(GTCCR); 00120 __DECLARE_8BIT_REGISTER__(EEARH); 00121 __DECLARE_8BIT_REGISTER__(EEARL); 00122 __DECLARE_8BIT_REGISTER__(EEDR); 00123 __DECLARE_8BIT_REGISTER__(EECR); 00124 __DECLARE_8BIT_REGISTER__(GPIOR0); 00125 __DECLARE_8BIT_REGISTER__(EIMSK); 00126 __DECLARE_8BIT_REGISTER__(EIFR); 00127 __DECLARE_8BIT_REGISTER__(PCIFR); 00128 __DECLARE_8BIT_REGISTER__(TIFR2); 00129 __DECLARE_8BIT_REGISTER__(TIFR1); 00130 __DECLARE_8BIT_REGISTER__(TIFR0); 00131 __DECLARE_8BIT_REGISTER__(PORTD); 00132 __DECLARE_8BIT_REGISTER__(DDRD); 00133 __DECLARE_8BIT_REGISTER__(PIND); 00134 __DECLARE_8BIT_REGISTER__(PORTC); 00135 __DECLARE_8BIT_REGISTER__(DDRC); 00136 __DECLARE_8BIT_REGISTER__(PINC); 00137 __DECLARE_8BIT_REGISTER__(PORTB); 00138 __DECLARE_8BIT_REGISTER__(DDRB); 00139 __DECLARE_8BIT_REGISTER__(PINB); 00140 __DECLARE_8BIT_REGISTER__(PORTA); 00141 __DECLARE_8BIT_REGISTER__(DDRA); 00142 __DECLARE_16BIT_REGISTER__(OCR1B); 00143 __DECLARE_16BIT_REGISTER__(OCR1A); 00144 __DECLARE_16BIT_REGISTER__(ICR1); 00145 __DECLARE_16BIT_REGISTER__(TCNT1); 00146 __DECLARE_16BIT_REGISTER__(ADC); 00147 __DECLARE_16BIT_REGISTER__(SP); 00148 00149 } // namespace AVRCpp 00150 00151 00152 // UCSR0C 00153 #define _UMSEL01 0x80 00154 #define _UMSEL00 0x40 00155 #define _UPM01 0x20 00156 #define _UPM00 0x10 00157 #define _USBS0 0x8 00158 #define _UCSZ01 0x4 00159 #define _UCSZ00 0x2 00160 #define _UCPOL0 0x1 00161 00162 // UCSR0B 00163 #define _RXCIE0 0x80 00164 #define _TXCIE0 0x40 00165 #define _UDRIE0 0x20 00166 #define _RXEN0 0x10 00167 #define _TXEN0 0x8 00168 #define _UCSZ02 0x4 00169 #define _RXB80 0x2 00170 #define _TXB80 0x1 00171 00172 // UCSR0A 00173 #define _RXC0 0x80 00174 #define _TXC0 0x40 00175 #define _UDRE0 0x20 00176 #define _FE0 0x10 00177 #define _DOR0 0x8 00178 #define _UPE0 0x4 00179 #define _U2X0 0x2 00180 #define _MPCM0 0x1 00181 00182 // TWAMR 00183 #define _TWAM6 0x80 00184 #define _TWAM5 0x40 00185 #define _TWAM4 0x20 00186 #define _TWAM3 0x10 00187 #define _TWAM2 0x8 00188 #define _TWAM1 0x4 00189 #define _TWAM0 0x2 00190 00191 // TWCR 00192 #define _TWINT 0x80 00193 #define _TWEA 0x40 00194 #define _TWSTA 0x20 00195 #define _TWSTO 0x10 00196 #define _TWWC 0x8 00197 #define _TWEN 0x4 00198 #define _TWIE 0x1 00199 00200 // TWAR 00201 #define _TWA6 0x80 00202 #define _TWA5 0x40 00203 #define _TWA4 0x20 00204 #define _TWA3 0x10 00205 #define _TWA2 0x8 00206 #define _TWA1 0x4 00207 #define _TWA0 0x2 00208 #define _TWGCE 0x1 00209 00210 // TWSR 00211 #define _TWS7 0x80 00212 #define _TWS6 0x40 00213 #define _TWS5 0x20 00214 #define _TWS4 0x10 00215 #define _TWS3 0x8 00216 #define _TWPS1 0x2 00217 #define _TWPS0 0x1 00218 00219 // ASSR 00220 #define _EXCLK 0x40 00221 #define _AS2 0x20 00222 #define _TCN2UB 0x10 00223 #define _OCR2AUB 0x8 00224 #define _OCR2BUB 0x4 00225 #define _TCR2AUB 0x2 00226 #define _TCR2BUB 0x1 00227 00228 // TCCR2B 00229 #define _FOC2A 0x80 00230 #define _FOC2B 0x40 00231 #define _WGM22 0x8 00232 #define _CS22 0x4 00233 #define _CS21 0x2 00234 #define _CS20 0x1 00235 00236 // TCCR2A 00237 #define _COM2A1 0x80 00238 #define _COM2A0 0x40 00239 #define _COM2B1 0x20 00240 #define _COM2B0 0x10 00241 #define _WGM21 0x2 00242 #define _WGM20 0x1 00243 00244 // TCCR1C 00245 #define _FOC1A 0x80 00246 #define _FOC1B 0x40 00247 00248 // TCCR1B 00249 #define _ICNC1 0x80 00250 #define _ICES1 0x40 00251 #define _WGM13 0x10 00252 #define _WGM12 0x8 00253 #define _CS12 0x4 00254 #define _CS11 0x2 00255 #define _CS10 0x1 00256 00257 // TCCR1A 00258 #define _COM1A1 0x80 00259 #define _COM1A0 0x40 00260 #define _COM1B1 0x20 00261 #define _COM1B0 0x10 00262 #define _WGM11 0x2 00263 #define _WGM10 0x1 00264 00265 // DIDR1 00266 #define _AIN1D 0x2 00267 #define _AIN0D 0x1 00268 00269 // DIDR0 00270 #define _ADC7D 0x80 00271 #define _ADC6D 0x40 00272 #define _ADC5D 0x20 00273 #define _ADC4D 0x10 00274 #define _ADC3D 0x8 00275 #define _ADC2D 0x4 00276 #define _ADC1D 0x2 00277 #define _ADC0D 0x1 00278 00279 // ADMUX 00280 #define _REFS1 0x80 00281 #define _REFS0 0x40 00282 #define _ADLAR 0x20 00283 #define _MUX4 0x10 00284 #define _MUX3 0x8 00285 #define _MUX2 0x4 00286 #define _MUX1 0x2 00287 #define _MUX0 0x1 00288 00289 // ADCSRB 00290 #define _ACME 0x40 00291 #define _ADTS2 0x4 00292 #define _ADTS1 0x2 00293 #define _ADTS0 0x1 00294 00295 // ADCSRA 00296 #define _ADEN 0x80 00297 #define _ADSC 0x40 00298 #define _ADATE 0x20 00299 #define _ADIF 0x10 00300 #define _ADIE 0x8 00301 #define _ADPS2 0x4 00302 #define _ADPS1 0x2 00303 #define _ADPS0 0x1 00304 00305 // PCMSK3 00306 #define _PCINT31 0x80 00307 #define _PCINT30 0x40 00308 #define _PCINT29 0x20 00309 #define _PCINT28 0x10 00310 #define _PCINT27 0x8 00311 #define _PCINT26 0x4 00312 #define _PCINT25 0x2 00313 #define _PCINT24 0x1 00314 00315 // TIMSK2 00316 #define _OCIE2B 0x4 00317 #define _OCIE2A 0x2 00318 #define _TOIE2 0x1 00319 00320 // TIMSK1 00321 #define _ICIE1 0x20 00322 #define _OCIE1B 0x4 00323 #define _OCIE1A 0x2 00324 #define _TOIE1 0x1 00325 00326 // TIMSK0 00327 #define _OCIE0B 0x4 00328 #define _OCIE0A 0x2 00329 #define _TOIE0 0x1 00330 00331 // TIFR2 00332 #define _OCF2A _BV(OCF2A) 00333 #define _OCF2B _BV(OCF2B) 00334 #define _TOV2 _BV(TOV2) 00335 00336 // PCMSK2 00337 #define _PCINT23 0x80 00338 #define _PCINT22 0x40 00339 #define _PCINT21 0x20 00340 #define _PCINT20 0x10 00341 #define _PCINT19 0x8 00342 #define _PCINT18 0x4 00343 #define _PCINT17 0x2 00344 #define _PCINT16 0x1 00345 00346 // PCMSK1 00347 #define _PCINT15 0x80 00348 #define _PCINT14 0x40 00349 #define _PCINT13 0x20 00350 #define _PCINT12 0x10 00351 #define _PCINT11 0x8 00352 #define _PCINT10 0x4 00353 #define _PCINT9 0x2 00354 #define _PCINT8 0x1 00355 00356 // PCMSK0 00357 #define _PCINT7 0x80 00358 #define _PCINT6 0x40 00359 #define _PCINT5 0x20 00360 #define _PCINT4 0x10 00361 #define _PCINT3 0x8 00362 #define _PCINT2 0x4 00363 #define _PCINT1 0x2 00364 #define _PCINT0 0x1 00365 00366 // EICRA 00367 #define _ISC21 0x20 00368 #define _ISC20 0x10 00369 #define _ISC11 0x8 00370 #define _ISC10 0x4 00371 #define _ISC01 0x2 00372 #define _ISC00 0x1 00373 00374 // PCICR 00375 #define _PCIE3 0x8 00376 #define _PCIE2 0x4 00377 #define _PCIE1 0x2 00378 #define _PCIE0 0x1 00379 00380 // PRR 00381 #define _PRTWI 0x80 00382 #define _PRTIM2 0x40 00383 #define _PRTIM0 0x20 00384 #define _PRTIM1 0x8 00385 #define _PRSPI 0x4 00386 #define _PRUSART0 0x2 00387 #define _PRADC 0x1 00388 00389 // CLKPR 00390 #define _CLKPCE 0x80 00391 #define _CLKPS3 0x8 00392 #define _CLKPS2 0x4 00393 #define _CLKPS1 0x2 00394 #define _CLKPS0 0x1 00395 00396 // WDTCSR 00397 #define _WDIF 0x80 00398 #define _WDIE 0x40 00399 #define _WDP3 0x20 00400 #define _WDCE 0x10 00401 #define _WDE 0x8 00402 #define _WDP2 0x4 00403 #define _WDP1 0x2 00404 #define _WDP0 0x1 00405 00406 // SREG 00407 #define _SREG_I 0x80 00408 #define _SREG_T 0x40 00409 #define _SREG_H 0x20 00410 #define _SREG_S 0x10 00411 #define _SREG_V 0x8 00412 #define _SREG_N 0x4 00413 #define _SREG_Z 0x2 00414 #define _SREG_C 0x1 00415 00416 // SPH 00417 #define _SP15 0x80 00418 #define _SP14 0x40 00419 #define _SP13 0x20 00420 #define _SP12 0x10 00421 #define _SP11 0x8 00422 #define _SP10 0x4 00423 #define _SP9 0x2 00424 #define _SP8 0x1 00425 00426 // SPL 00427 #define _SP7 0x80 00428 #define _SP6 0x40 00429 #define _SP5 0x20 00430 #define _SP4 0x10 00431 #define _SP3 0x8 00432 #define _SP2 0x4 00433 #define _SP1 0x2 00434 #define _SP0 0x1 00435 00436 // SPMCSR 00437 #define _SPMIE 0x80 00438 #define _RWWSB 0x40 00439 #define _SIGRD 0x20 00440 #define _RWWSRE 0x10 00441 #define _BLBSET 0x8 00442 #define _PGWRT 0x4 00443 #define _PGERS 0x2 00444 #define _SPMEN 0x1 00445 00446 // MCUCR 00447 #define _JTD 0x80 00448 #define _PUD 0x10 00449 #define _IVSEL 0x2 00450 #define _IVCE 0x1 00451 00452 // MCUSR 00453 #define _JTRF 0x10 00454 #define _WDRF 0x8 00455 #define _BORF 0x4 00456 #define _EXTRF 0x2 00457 #define _PORF 0x1 00458 00459 // SMCR 00460 #define _SM2 0x8 00461 #define _SM1 0x4 00462 #define _SM0 0x2 00463 #define _SE 0x1 00464 00465 // ACSR 00466 #define _ACD 0x80 00467 #define _ACBG 0x40 00468 #define _ACO 0x20 00469 #define _ACI 0x10 00470 #define _ACIE 0x8 00471 #define _ACIC 0x4 00472 #define _ACIS1 0x2 00473 #define _ACIS0 0x1 00474 00475 // SPSR 00476 #define _SPIF 0x80 00477 #define _WCOL 0x40 00478 #define _SPI2X 0x1 00479 00480 // SPCR 00481 #define _SPIE 0x80 00482 #define _SPE 0x40 00483 #define _DORD 0x20 00484 #define _MSTR 0x10 00485 #define _CPOL 0x8 00486 #define _CPHA 0x4 00487 #define _SPR1 0x2 00488 #define _SPR0 0x1 00489 00490 // TCCR0B 00491 #define _FOC0A 0x80 00492 #define _FOC0B 0x40 00493 #define _WGM02 0x8 00494 #define _CS02 0x4 00495 #define _CS01 0x2 00496 #define _CS00 0x1 00497 00498 // TCCR0A 00499 #define _COM0A1 0x80 00500 #define _COM0A0 0x40 00501 #define _COM0B1 0x20 00502 #define _COM0B0 0x10 00503 #define _WGM01 0x2 00504 #define _WGM00 0x1 00505 00506 // GTCCR 00507 #define _TSM 0x80 00508 #define _PSRASY 0x2 00509 #define _PSRSYNC 0x1 00510 00511 // EECR 00512 #define _EEPM1 0x20 00513 #define _EEPM0 0x10 00514 #define _EERIE 0x8 00515 #define _EEMPE 0x4 00516 #define _EEPE 0x2 00517 #define _EERE 0x1 00518 00519 // EIMSK 00520 #define _INT2 0x4 00521 #define _INT1 0x2 00522 #define _INT0 0x1 00523 00524 // EIFR 00525 #define _INTF2 0x4 00526 #define _INTF1 0x2 00527 #define _INTF0 0x1 00528 00529 // PCIFR 00530 #define _PCIF3 0x8 00531 #define _PCIF2 0x4 00532 #define _PCIF1 0x2 00533 #define _PCIF0 0x1 00534 00535 // TIFR1 00536 #define _ICF1 0x20 00537 #define _OCF1B 0x4 00538 #define _OCF1A 0x2 00539 #define _TOV1 0x1 00540 00541 // TIFR0 00542 #define _OCF0B 0x4 00543 #define _OCF0A 0x2 00544 #define _TOV0 0x1 00545 00546 // PORTD 00547 #define _PD7 0x80 00548 #define _PD6 0x40 00549 #define _PD5 0x20 00550 #define _PD4 0x10 00551 #define _PD3 0x8 00552 #define _PD2 0x4 00553 #define _PD1 0x2 00554 #define _PD0 0x1 00555 00556 // DDRD 00557 #define _DDD7 0x80 00558 #define _DDD6 0x40 00559 #define _DDD5 0x20 00560 #define _DDD4 0x10 00561 #define _DDD3 0x8 00562 #define _DDD2 0x4 00563 #define _DDD1 0x2 00564 #define _DDD0 0x1 00565 00566 // PIND 00567 #define _PIND7 0x80 00568 #define _PIND6 0x40 00569 #define _PIND5 0x20 00570 #define _PIND4 0x10 00571 #define _PIND3 0x8 00572 #define _PIND2 0x4 00573 #define _PIND1 0x2 00574 #define _PIND0 0x1 00575 00576 // PORTC 00577 #define _PC7 0x80 00578 #define _PC6 0x40 00579 #define _PC5 0x20 00580 #define _PC4 0x10 00581 #define _PC3 0x8 00582 #define _PC2 0x4 00583 #define _PC1 0x2 00584 #define _PC0 0x1 00585 00586 // DDRC 00587 #define _DDC7 0x80 00588 #define _DDC6 0x40 00589 #define _DDC5 0x20 00590 #define _DDC4 0x10 00591 #define _DDC3 0x8 00592 #define _DDC2 0x4 00593 #define _DDC1 0x2 00594 #define _DDC0 0x1 00595 00596 // PINC 00597 #define _PINC7 0x80 00598 #define _PINC6 0x40 00599 #define _PINC5 0x20 00600 #define _PINC4 0x10 00601 #define _PINC3 0x8 00602 #define _PINC2 0x4 00603 #define _PINC1 0x2 00604 #define _PINC0 0x1 00605 00606 // PORTB 00607 #define _PB7 0x80 00608 #define _PB6 0x40 00609 #define _PB5 0x20 00610 #define _PB4 0x10 00611 #define _PB3 0x8 00612 #define _PB2 0x4 00613 #define _PB1 0x2 00614 #define _PB0 0x1 00615 00616 // DDRB 00617 #define _DDB7 0x80 00618 #define _DDB6 0x40 00619 #define _DDB5 0x20 00620 #define _DDB4 0x10 00621 #define _DDB3 0x8 00622 #define _DDB2 0x4 00623 #define _DDB1 0x2 00624 #define _DDB0 0x1 00625 00626 // PINB 00627 #define _PINB7 0x80 00628 #define _PINB6 0x40 00629 #define _PINB5 0x20 00630 #define _PINB4 0x10 00631 #define _PINB3 0x8 00632 #define _PINB2 0x4 00633 #define _PINB1 0x2 00634 #define _PINB0 0x1 00635 00636 // PORTA 00637 #define _PA7 0x80 00638 #define _PA6 0x40 00639 #define _PA5 0x20 00640 #define _PA4 0x10 00641 #define _PA3 0x8 00642 #define _PA2 0x4 00643 #define _PA1 0x2 00644 #define _PA0 0x1 00645 00646 // DDRA 00647 #define _DDA7 0x80 00648 #define _DDA6 0x40 00649 #define _DDA5 0x20 00650 #define _DDA4 0x10 00651 #define _DDA3 0x8 00652 #define _DDA2 0x4 00653 #define _DDA1 0x2 00654 #define _DDA0 0x1 00655 00656 00657 // General ports 00658 namespace AVRCpp 00659 { 00660 __DECLARE_PORT__(D); 00661 __DECLARE_PORT__(C); 00662 __DECLARE_PORT__(B); 00663 __DECLARE_PORT__(A); 00664 00665 } // namespace AVRCpp 00666 00667 00668 /**********************************************************************************************************************/ 00669 00670 #endif // ifndef __AVR_CPP_IO_H__ 00671 #endif // ifndef __AVR_CPP_ATMEGA644_IO_H__
1.5.2
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 MTÜ TTÜ Robotiklubi
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