00001 /**********************************************************************************************************************\ 00002 00003 C++ library for Atmel AVR microcontrollers 00004 Copyright (C) 2007 Lauri Kirikal, Mikk Leini, Rasmus Raag, MTU TTU Robotiklubi 00005 00006 This program is free software; you can redistribute it and/or 00007 modify it under the terms of the GNU General Public License 00008 as published by the Free Software Foundation; either version 2 00009 of the License, or (at your option) any later version. 00010 00011 This program is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program; if not, write to the Free Software 00018 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00019 00020 See http://creativecommons.org/licenses/GPL/2.0/ 00021 00022 MTU TTU Robotiklubi http://www.robotiklubi.ee robotiklubi@gmail.com 00023 Lauri Kirikal laurikirikal@gmail.com 00024 Mikk Leini mikk.leini@gmail.com 00025 00026 \**********************************************************************************************************************/ 00027 00028 #ifndef __AVR_CPP_ATMEGA48_IO_H__ 00029 #define __AVR_CPP_ATMEGA48_IO_H__ 00030 00031 #if defined(__DOXYGEN__) && !defined(__AVR_CPP_IO_H__) 00032 #include <avr/cpp/IO.h> 00033 #endif 00034 00035 #ifndef __AVR_CPP_IO_H__ 00036 #error "Include <avr/cpp/IO.h> instead of <avr/cpp/atmega48/IO.h>." 00037 #else 00038 00039 00040 /**********************************************************************************************************************\ 00041 00042 atmega48 registers, bits and ports declarations. 00043 This file is generated. Do not modify manually. 00044 00045 \**********************************************************************************************************************/ 00046 00047 // Registers 00048 namespace AVRCpp 00049 { 00050 __DECLARE_8BIT_REGISTER__(UDR0); 00051 __DECLARE_8BIT_REGISTER__(UBRR0H); 00052 __DECLARE_8BIT_REGISTER__(UBRR0L); 00053 __DECLARE_8BIT_REGISTER__(UCSR0C); 00054 __DECLARE_8BIT_REGISTER__(UCSR0B); 00055 __DECLARE_8BIT_REGISTER__(UCSR0A); 00056 __DECLARE_8BIT_REGISTER__(TWAMR); 00057 __DECLARE_8BIT_REGISTER__(TWCR); 00058 __DECLARE_8BIT_REGISTER__(TWDR); 00059 __DECLARE_8BIT_REGISTER__(TWAR); 00060 __DECLARE_8BIT_REGISTER__(TWSR); 00061 __DECLARE_8BIT_REGISTER__(TWBR); 00062 __DECLARE_8BIT_REGISTER__(ASSR); 00063 __DECLARE_8BIT_REGISTER__(OCR2B); 00064 __DECLARE_8BIT_REGISTER__(OCR2A); 00065 __DECLARE_8BIT_REGISTER__(TCNT2); 00066 __DECLARE_8BIT_REGISTER__(TCCR2B); 00067 __DECLARE_8BIT_REGISTER__(TCCR2A); 00068 __DECLARE_8BIT_REGISTER__(OCR1BH); 00069 __DECLARE_8BIT_REGISTER__(OCR1BL); 00070 __DECLARE_8BIT_REGISTER__(OCR1AH); 00071 __DECLARE_8BIT_REGISTER__(OCR1AL); 00072 __DECLARE_8BIT_REGISTER__(ICR1H); 00073 __DECLARE_8BIT_REGISTER__(ICR1L); 00074 __DECLARE_8BIT_REGISTER__(TCNT1H); 00075 __DECLARE_8BIT_REGISTER__(TCNT1L); 00076 __DECLARE_8BIT_REGISTER__(TCCR1C); 00077 __DECLARE_8BIT_REGISTER__(TCCR1B); 00078 __DECLARE_8BIT_REGISTER__(TCCR1A); 00079 __DECLARE_8BIT_REGISTER__(DIDR1); 00080 __DECLARE_8BIT_REGISTER__(DIDR0); 00081 __DECLARE_8BIT_REGISTER__(ADMUX); 00082 __DECLARE_8BIT_REGISTER__(ADCSRB); 00083 __DECLARE_8BIT_REGISTER__(ADCSRA); 00084 __DECLARE_8BIT_REGISTER__(ADCH); 00085 __DECLARE_8BIT_REGISTER__(ADCL); 00086 __DECLARE_8BIT_REGISTER__(TIMSK2); 00087 __DECLARE_8BIT_REGISTER__(TIMSK1); 00088 __DECLARE_8BIT_REGISTER__(TIMSK0); 00089 __DECLARE_8BIT_REGISTER__(PCMSK2); 00090 __DECLARE_8BIT_REGISTER__(PCMSK1); 00091 __DECLARE_8BIT_REGISTER__(PCMSK0); 00092 __DECLARE_8BIT_REGISTER__(EICRA); 00093 __DECLARE_8BIT_REGISTER__(PCICR); 00094 __DECLARE_8BIT_REGISTER__(OSCCAL); 00095 __DECLARE_8BIT_REGISTER__(PRR); 00096 __DECLARE_8BIT_REGISTER__(CLKPR); 00097 __DECLARE_8BIT_REGISTER__(WDTCSR); 00098 __DECLARE_8BIT_REGISTER__(SREG); 00099 __DECLARE_8BIT_REGISTER__(SPH); 00100 __DECLARE_8BIT_REGISTER__(SPL); 00101 __DECLARE_8BIT_REGISTER__(SPMCSR); 00102 __DECLARE_8BIT_REGISTER__(MCUCR); 00103 __DECLARE_8BIT_REGISTER__(MCUSR); 00104 __DECLARE_8BIT_REGISTER__(SMCR); 00105 __DECLARE_8BIT_REGISTER__(ACSR); 00106 __DECLARE_8BIT_REGISTER__(SPDR); 00107 __DECLARE_8BIT_REGISTER__(SPSR); 00108 __DECLARE_8BIT_REGISTER__(SPCR); 00109 __DECLARE_8BIT_REGISTER__(GPIOR2); 00110 __DECLARE_8BIT_REGISTER__(GPIOR1); 00111 __DECLARE_8BIT_REGISTER__(OCR0B); 00112 __DECLARE_8BIT_REGISTER__(OCR0A); 00113 __DECLARE_8BIT_REGISTER__(TCNT0); 00114 __DECLARE_8BIT_REGISTER__(TCCR0B); 00115 __DECLARE_8BIT_REGISTER__(TCCR0A); 00116 __DECLARE_8BIT_REGISTER__(GTCCR); 00117 __DECLARE_8BIT_REGISTER__(EEARH); 00118 __DECLARE_8BIT_REGISTER__(EEARL); 00119 __DECLARE_8BIT_REGISTER__(EEDR); 00120 __DECLARE_8BIT_REGISTER__(EECR); 00121 __DECLARE_8BIT_REGISTER__(GPIOR0); 00122 __DECLARE_8BIT_REGISTER__(EIMSK); 00123 __DECLARE_8BIT_REGISTER__(EIFR); 00124 __DECLARE_8BIT_REGISTER__(PCIFR); 00125 __DECLARE_8BIT_REGISTER__(TIFR2); 00126 __DECLARE_8BIT_REGISTER__(TIFR1); 00127 __DECLARE_8BIT_REGISTER__(TIFR0); 00128 __DECLARE_8BIT_REGISTER__(PORTD); 00129 __DECLARE_8BIT_REGISTER__(DDRD); 00130 __DECLARE_8BIT_REGISTER__(PIND); 00131 __DECLARE_8BIT_REGISTER__(PORTC); 00132 __DECLARE_8BIT_REGISTER__(DDRC); 00133 __DECLARE_8BIT_REGISTER__(PINC); 00134 __DECLARE_8BIT_REGISTER__(PORTB); 00135 __DECLARE_8BIT_REGISTER__(DDRB); 00136 __DECLARE_8BIT_REGISTER__(PINB); 00137 __DECLARE_16BIT_REGISTER__(UBRR0); 00138 __DECLARE_16BIT_REGISTER__(OCR1B); 00139 __DECLARE_16BIT_REGISTER__(OCR1A); 00140 __DECLARE_16BIT_REGISTER__(ICR1); 00141 __DECLARE_16BIT_REGISTER__(TCNT1); 00142 __DECLARE_16BIT_REGISTER__(ADC); 00143 __DECLARE_16BIT_REGISTER__(EEAR); 00144 00145 } // namespace AVRCpp 00146 00147 00148 // UCSR0C 00149 #define _UMSEL01 0x80 00150 #define _UMSEL00 0x40 00151 #define _UPM01 0x20 00152 #define _UPM00 0x10 00153 #define _USBS0 0x8 00154 #define _UCSZ01 0x4 00155 #define _UDORD0 0x2 00156 #define _UCSZ00 0x1 00157 00158 // UCSR0B 00159 #define _RXCIE0 0x80 00160 #define _TXCIE0 0x40 00161 #define _UDRIE0 0x20 00162 #define _RXEN0 0x10 00163 #define _TXEN0 0x8 00164 #define _UCSZ02 0x4 00165 #define _RXB80 0x2 00166 #define _TXB80 0x1 00167 00168 // UCSR0A 00169 #define _RXC0 0x80 00170 #define _TXC0 0x40 00171 #define _UDRE0 0x20 00172 #define _FE0 0x10 00173 #define _DOR0 0x8 00174 #define _UPE0 0x4 00175 #define _U2X0 0x2 00176 #define _MPCM0 0x1 00177 00178 // TWAMR 00179 #define _TWAM6 0x80 00180 #define _TWAM5 0x40 00181 #define _TWAM4 0x20 00182 #define _TWAM3 0x10 00183 #define _TWAM2 0x8 00184 #define _TWAM1 0x4 00185 #define _TWAM0 0x2 00186 00187 // TWCR 00188 #define _TWINT 0x80 00189 #define _TWEA 0x40 00190 #define _TWSTA 0x20 00191 #define _TWSTO 0x10 00192 #define _TWWC 0x8 00193 #define _TWEN 0x4 00194 #define _TWIE 0x1 00195 00196 // TWAR 00197 #define _TWA6 0x80 00198 #define _TWA5 0x40 00199 #define _TWA4 0x20 00200 #define _TWA3 0x10 00201 #define _TWA2 0x8 00202 #define _TWA1 0x4 00203 #define _TWA0 0x2 00204 #define _TWGCE 0x1 00205 00206 // TWSR 00207 #define _TWS7 0x80 00208 #define _TWS6 0x40 00209 #define _TWS5 0x20 00210 #define _TWS4 0x10 00211 #define _TWS3 0x8 00212 #define _TWPS1 0x2 00213 #define _TWPS0 0x1 00214 00215 // ASSR 00216 #define _EXCLK 0x40 00217 #define _AS2 0x20 00218 #define _TCN2UB 0x10 00219 #define _OCR2AUB 0x8 00220 #define _OCR2BUB 0x4 00221 #define _TCR2AUB 0x2 00222 #define _TCR2BUB 0x1 00223 00224 // TCCR2B 00225 #define _FOC2A 0x80 00226 #define _FOC2B 0x40 00227 #define _WGM22 0x8 00228 #define _CS22 0x4 00229 #define _CS21 0x2 00230 #define _CS20 0x1 00231 00232 // TCCR2A 00233 #define _COM2A1 0x80 00234 #define _COM2A0 0x40 00235 #define _COM2B1 0x20 00236 #define _COM2B0 0x10 00237 #define _WGM21 0x2 00238 #define _WGM20 0x1 00239 00240 // TCCR1C 00241 #define _FOC1A 0x80 00242 #define _FOC1B 0x40 00243 00244 // TCCR1B 00245 #define _ICNC1 0x80 00246 #define _ICES1 0x40 00247 #define _WGM13 0x10 00248 #define _WGM12 0x8 00249 #define _CS12 0x4 00250 #define _CS11 0x2 00251 #define _CS10 0x1 00252 00253 // TCCR1A 00254 #define _COM1A1 0x80 00255 #define _COM1A0 0x40 00256 #define _COM1B1 0x20 00257 #define _COM1B0 0x10 00258 #define _WGM11 0x2 00259 #define _WGM10 0x1 00260 00261 // DIDR1 00262 #define _AIN1D 0x2 00263 #define _AIN0D 0x1 00264 00265 // DIDR0 00266 #define _ADC5D 0x20 00267 #define _ADC4D 0x10 00268 #define _ADC3D 0x8 00269 #define _ADC2D 0x4 00270 #define _ADC1D 0x2 00271 #define _ADC0D 0x1 00272 00273 // ADMUX 00274 #define _REFS1 0x80 00275 #define _REFS0 0x40 00276 #define _ADLAR 0x20 00277 #define _MUX3 0x8 00278 #define _MUX2 0x4 00279 #define _MUX1 0x2 00280 #define _MUX0 0x1 00281 00282 // ADCSRB 00283 #define _ACME 0x40 00284 #define _ADTS2 0x4 00285 #define _ADTS1 0x2 00286 #define _ADTS0 0x1 00287 00288 // ADCSRA 00289 #define _ADEN 0x80 00290 #define _ADSC 0x40 00291 #define _ADATE 0x20 00292 #define _ADIF 0x10 00293 #define _ADIE 0x8 00294 #define _ADPS2 0x4 00295 #define _ADPS1 0x2 00296 #define _ADPS0 0x1 00297 00298 // TIMSK2 00299 #define _OCIE2B 0x4 00300 #define _OCIE2A 0x2 00301 #define _TOIE2 0x1 00302 00303 // TIMSK1 00304 #define _ICIE1 0x20 00305 #define _OCIE1B 0x4 00306 #define _OCIE1A 0x2 00307 #define _TOIE1 0x1 00308 00309 // TIMSK0 00310 #define _OCIE0B 0x4 00311 #define _OCIE0A 0x2 00312 #define _TOIE0 0x1 00313 00314 // PCMSK2 00315 #define _PCINT23 0x80 00316 #define _PCINT22 0x40 00317 #define _PCINT21 0x20 00318 #define _PCINT20 0x10 00319 #define _PCINT19 0x8 00320 #define _PCINT18 0x4 00321 #define _PCINT17 0x2 00322 #define _PCINT16 0x1 00323 00324 // PCMSK1 00325 #define _PCINT14 0x40 00326 #define _PCINT13 0x20 00327 #define _PCINT12 0x10 00328 #define _PCINT11 0x8 00329 #define _PCINT10 0x4 00330 #define _PCINT9 0x2 00331 #define _PCINT8 0x1 00332 00333 // PCMSK0 00334 #define _PCINT7 0x80 00335 #define _PCINT6 0x40 00336 #define _PCINT5 0x20 00337 #define _PCINT4 0x10 00338 #define _PCINT3 0x8 00339 #define _PCINT2 0x4 00340 #define _PCINT1 0x2 00341 #define _PCINT0 0x1 00342 00343 // EICRA 00344 #define _ISC11 0x8 00345 #define _ISC10 0x4 00346 #define _ISC01 0x2 00347 #define _ISC00 0x1 00348 00349 // PCICR 00350 #define _PCIE2 0x4 00351 #define _PCIE1 0x2 00352 #define _PCIE0 0x1 00353 00354 // PRR 00355 #define _PRTWI 0x80 00356 #define _PRTIM2 0x40 00357 #define _PRTIM0 0x20 00358 #define _PRTIM1 0x8 00359 #define _PRSPI 0x4 00360 #define _PRUSART0 0x2 00361 #define _PRADC 0x1 00362 00363 // CLKPR 00364 #define _CLKPCE 0x80 00365 #define _CLKPS3 0x8 00366 #define _CLKPS2 0x4 00367 #define _CLKPS1 0x2 00368 #define _CLKPS0 0x1 00369 00370 // WDTCSR 00371 #define _WDIF 0x80 00372 #define _WDIE 0x40 00373 #define _WDP3 0x20 00374 #define _WDCE 0x10 00375 #define _WDE 0x8 00376 #define _WDP2 0x4 00377 #define _WDP1 0x2 00378 #define _WDP0 0x1 00379 00380 // SREG 00381 #define _SREG_I 0x80 00382 #define _SREG_T 0x40 00383 #define _SREG_H 0x20 00384 #define _SREG_S 0x10 00385 #define _SREG_V 0x8 00386 #define _SREG_N 0x4 00387 #define _SREG_Z 0x2 00388 #define _SREG_C 0x1 00389 00390 // SPL 00391 #define _SP7 0x80 00392 #define _SP6 0x40 00393 #define _SP5 0x20 00394 #define _SP4 0x10 00395 #define _SP3 0x8 00396 #define _SP2 0x4 00397 #define _SP1 0x2 00398 #define _SP0 0x1 00399 00400 // SPMCSR 00401 #define _SPMIE 0x80 00402 #define _RWWSB 0x40 00403 #define _RWWSRE 0x10 00404 #define _BLBSET 0x8 00405 #define _PGWRT 0x4 00406 #define _PGERS 0x2 00407 #define _SELFPRGEN 0x1 00408 00409 // MCUCR 00410 #define _PUD 0x10 00411 #define _IVSEL 0x2 00412 #define _IVCE 0x1 00413 00414 // MCUSR 00415 #define _WDRF 0x8 00416 #define _BORF 0x4 00417 #define _EXTRF 0x2 00418 #define _PORF 0x1 00419 00420 // SMCR 00421 #define _SM2 0x8 00422 #define _SM1 0x4 00423 #define _SM0 0x2 00424 #define _SE 0x1 00425 00426 // ACSR 00427 #define _ACD 0x80 00428 #define _ACBG 0x40 00429 #define _ACO 0x20 00430 #define _ACI 0x10 00431 #define _ACIE 0x8 00432 #define _ACIC 0x4 00433 #define _ACIS1 0x2 00434 #define _ACIS0 0x1 00435 00436 // SPSR 00437 #define _SPIF 0x80 00438 #define _WCOL 0x40 00439 #define _SPI2X 0x1 00440 00441 // SPCR 00442 #define _SPIE 0x80 00443 #define _SPE 0x40 00444 #define _DORD 0x20 00445 #define _MSTR 0x10 00446 #define _CPOL 0x8 00447 #define _CPHA 0x4 00448 #define _SPR1 0x2 00449 #define _SPR0 0x1 00450 00451 // TCCR0B 00452 #define _FOC0A 0x80 00453 #define _FOC0B 0x40 00454 #define _WGM02 0x8 00455 #define _CS02 0x4 00456 #define _CS01 0x2 00457 #define _CS00 0x1 00458 00459 // TCCR0A 00460 #define _COM0A1 0x80 00461 #define _COM0A0 0x40 00462 #define _COM0B1 0x20 00463 #define _COM0B0 0x10 00464 #define _WGM01 0x2 00465 #define _WGM00 0x1 00466 00467 // GTCCR 00468 #define _TSM 0x80 00469 #define _PSRASY 0x2 00470 #define _PSRSYNC 0x1 00471 00472 // EECR 00473 #define _EEPM1 0x20 00474 #define _EEPM0 0x10 00475 #define _EERIE 0x8 00476 #define _EEMPE 0x4 00477 #define _EEPE 0x2 00478 #define _EERE 0x1 00479 00480 // EIMSK 00481 #define _INT1 0x2 00482 #define _INT0 0x1 00483 00484 // EIFR 00485 #define _INTF1 0x2 00486 #define _INTF0 0x1 00487 00488 // PCIFR 00489 #define _PCIF2 0x4 00490 #define _PCIF1 0x2 00491 #define _PCIF0 0x1 00492 00493 // TIFR2 00494 #define _OCF2B 0x4 00495 #define _OCF2A 0x2 00496 #define _TOV2 0x1 00497 00498 // TIFR1 00499 #define _ICF1 0x20 00500 #define _OCF1B 0x4 00501 #define _OCF1A 0x2 00502 #define _TOV1 0x1 00503 00504 // TIFR0 00505 #define _OCF0B 0x4 00506 #define _OCF0A 0x2 00507 #define _TOV0 0x1 00508 00509 // PORTD 00510 #define _PD7 0x80 00511 #define _PD6 0x40 00512 #define _PD5 0x20 00513 #define _PD4 0x10 00514 #define _PD3 0x8 00515 #define _PD2 0x4 00516 #define _PD1 0x2 00517 #define _PD0 0x1 00518 00519 // DDRD 00520 #define _DDD7 0x80 00521 #define _DDD6 0x40 00522 #define _DDD5 0x20 00523 #define _DDD4 0x10 00524 #define _DDD3 0x8 00525 #define _DDD2 0x4 00526 #define _DDD1 0x2 00527 #define _DDD0 0x1 00528 00529 // PIND 00530 #define _PIND7 0x80 00531 #define _PIND6 0x40 00532 #define _PIND5 0x20 00533 #define _PIND4 0x10 00534 #define _PIND3 0x8 00535 #define _PIND2 0x4 00536 #define _PIND1 0x2 00537 #define _PIND0 0x1 00538 00539 // PORTC 00540 #define _PC6 0x40 00541 #define _PC5 0x20 00542 #define _PC4 0x10 00543 #define _PC3 0x8 00544 #define _PC2 0x4 00545 #define _PC1 0x2 00546 #define _PC0 0x1 00547 00548 // DDRC 00549 #define _DDC6 0x40 00550 #define _DDC5 0x20 00551 #define _DDC4 0x10 00552 #define _DDC3 0x8 00553 #define _DDC2 0x4 00554 #define _DDC1 0x2 00555 #define _DDC0 0x1 00556 00557 // PINC 00558 #define _PINC6 0x40 00559 #define _PINC5 0x20 00560 #define _PINC4 0x10 00561 #define _PINC3 0x8 00562 #define _PINC2 0x4 00563 #define _PINC1 0x2 00564 #define _PINC0 0x1 00565 00566 // PORTB 00567 #define _PB7 0x80 00568 #define _PB6 0x40 00569 #define _PB5 0x20 00570 #define _PB4 0x10 00571 #define _PB3 0x8 00572 #define _PB2 0x4 00573 #define _PB1 0x2 00574 #define _PB0 0x1 00575 00576 // DDRB 00577 #define _DDB7 0x80 00578 #define _DDB6 0x40 00579 #define _DDB5 0x20 00580 #define _DDB4 0x10 00581 #define _DDB3 0x8 00582 #define _DDB2 0x4 00583 #define _DDB1 0x2 00584 #define _DDB0 0x1 00585 00586 // PINB 00587 #define _PINB7 0x80 00588 #define _PINB6 0x40 00589 #define _PINB5 0x20 00590 #define _PINB4 0x10 00591 #define _PINB3 0x8 00592 #define _PINB2 0x4 00593 #define _PINB1 0x2 00594 #define _PINB0 0x1 00595 00596 00597 // General ports 00598 namespace AVRCpp 00599 { 00600 __DECLARE_PORT__(D); 00601 __DECLARE_PORT__(C); 00602 __DECLARE_PORT__(B); 00603 00604 } // namespace AVRCpp 00605 00606 00607 /**********************************************************************************************************************/ 00608 00609 #endif // ifndef __AVR_CPP_IO_H__ 00610 #endif // ifndef __AVR_CPP_ATMEGA48_IO_H__
1.5.2
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 MTÜ TTÜ Robotiklubi
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