00001 /**********************************************************************************************************************\ 00002 00003 C++ library for Atmel AVR microcontrollers 00004 Copyright (C) 2007 Lauri Kirikal, Mikk Leini, Rasmus Raag, MTU TTU Robotiklubi 00005 00006 This program is free software; you can redistribute it and/or 00007 modify it under the terms of the GNU General Public License 00008 as published by the Free Software Foundation; either version 2 00009 of the License, or (at your option) any later version. 00010 00011 This program is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program; if not, write to the Free Software 00018 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00019 00020 See http://creativecommons.org/licenses/GPL/2.0/ 00021 00022 MTU TTU Robotiklubi http://www.robotiklubi.ee robotiklubi@gmail.com 00023 Lauri Kirikal laurikirikal@gmail.com 00024 Mikk Leini mikk.leini@gmail.com 00025 00026 \**********************************************************************************************************************/ 00027 00028 #ifndef __AVR_CPP_ATMEGA324P_IO_H__ 00029 #define __AVR_CPP_ATMEGA324P_IO_H__ 00030 00031 #if defined(__DOXYGEN__) && !defined(__AVR_CPP_IO_H__) 00032 #include <avr/cpp/IO.h> 00033 #endif 00034 00035 #ifndef __AVR_CPP_IO_H__ 00036 #error "Include <avr/cpp/IO.h> instead of <avr/cpp/atmega324p/IO.h>." 00037 #else 00038 00039 00040 /**********************************************************************************************************************\ 00041 00042 atmega324 registers, bits and ports declarations. 00043 This file is generated. Do not modify manually. 00044 00045 \**********************************************************************************************************************/ 00046 00047 // Registers 00048 namespace AVRCpp 00049 { 00050 __DECLARE_8BIT_REGISTER__(PINA); 00051 __DECLARE_8BIT_REGISTER__(UDR1); 00052 __DECLARE_8BIT_REGISTER__(UBRR1H); 00053 __DECLARE_8BIT_REGISTER__(UBRR1L); 00054 __DECLARE_8BIT_REGISTER__(UCSR1C); 00055 __DECLARE_8BIT_REGISTER__(UCSR1B); 00056 __DECLARE_8BIT_REGISTER__(UCSR1A); 00057 __DECLARE_8BIT_REGISTER__(UDR0); 00058 __DECLARE_8BIT_REGISTER__(UBRR0H); 00059 __DECLARE_8BIT_REGISTER__(UBRR0L); 00060 __DECLARE_8BIT_REGISTER__(UCSR0C); 00061 __DECLARE_8BIT_REGISTER__(UCSR0B); 00062 __DECLARE_8BIT_REGISTER__(UCSR0A); 00063 __DECLARE_8BIT_REGISTER__(TWAMR); 00064 __DECLARE_8BIT_REGISTER__(TWCR); 00065 __DECLARE_8BIT_REGISTER__(TWDR); 00066 __DECLARE_8BIT_REGISTER__(TWAR); 00067 __DECLARE_8BIT_REGISTER__(TWSR); 00068 __DECLARE_8BIT_REGISTER__(TWBR); 00069 __DECLARE_8BIT_REGISTER__(ASSR); 00070 __DECLARE_8BIT_REGISTER__(OCR2B); 00071 __DECLARE_8BIT_REGISTER__(OCR2A); 00072 __DECLARE_8BIT_REGISTER__(TCNT2); 00073 __DECLARE_8BIT_REGISTER__(TCCR2B); 00074 __DECLARE_8BIT_REGISTER__(TCCR2A); 00075 __DECLARE_8BIT_REGISTER__(OCR1BH); 00076 __DECLARE_8BIT_REGISTER__(OCR1BL); 00077 __DECLARE_8BIT_REGISTER__(OCR1AH); 00078 __DECLARE_8BIT_REGISTER__(OCR1AL); 00079 __DECLARE_8BIT_REGISTER__(ICR1H); 00080 __DECLARE_8BIT_REGISTER__(ICR1L); 00081 __DECLARE_8BIT_REGISTER__(TCNT1H); 00082 __DECLARE_8BIT_REGISTER__(TCNT1L); 00083 __DECLARE_8BIT_REGISTER__(TCCR1C); 00084 __DECLARE_8BIT_REGISTER__(TCCR1B); 00085 __DECLARE_8BIT_REGISTER__(TCCR1A); 00086 __DECLARE_8BIT_REGISTER__(DIDR1); 00087 __DECLARE_8BIT_REGISTER__(DIDR0); 00088 __DECLARE_8BIT_REGISTER__(ADMUX); 00089 __DECLARE_8BIT_REGISTER__(ADCSRB); 00090 __DECLARE_8BIT_REGISTER__(ADCSRA); 00091 __DECLARE_8BIT_REGISTER__(ADCH); 00092 __DECLARE_8BIT_REGISTER__(ADCL); 00093 __DECLARE_8BIT_REGISTER__(PCMSK3); 00094 __DECLARE_8BIT_REGISTER__(TIMSK2); 00095 __DECLARE_8BIT_REGISTER__(TIMSK1); 00096 __DECLARE_8BIT_REGISTER__(TIMSK0); 00097 __DECLARE_8BIT_REGISTER__(PCMSK2); 00098 __DECLARE_8BIT_REGISTER__(PCMSK1); 00099 __DECLARE_8BIT_REGISTER__(PCMSK0); 00100 __DECLARE_8BIT_REGISTER__(EICRA); 00101 __DECLARE_8BIT_REGISTER__(PCICR); 00102 __DECLARE_8BIT_REGISTER__(OSCCAL); 00103 __DECLARE_8BIT_REGISTER__(PRR); 00104 __DECLARE_8BIT_REGISTER__(CLKPR); 00105 __DECLARE_8BIT_REGISTER__(WDTCSR); 00106 __DECLARE_8BIT_REGISTER__(SREG); 00107 __DECLARE_8BIT_REGISTER__(SPH); 00108 __DECLARE_8BIT_REGISTER__(SPL); 00109 __DECLARE_8BIT_REGISTER__(SPMCSR); 00110 __DECLARE_8BIT_REGISTER__(MCUCR); 00111 __DECLARE_8BIT_REGISTER__(MCUSR); 00112 __DECLARE_8BIT_REGISTER__(SMCR); 00113 __DECLARE_8BIT_REGISTER__(OCDR); 00114 __DECLARE_8BIT_REGISTER__(ACSR); 00115 __DECLARE_8BIT_REGISTER__(SPDR); 00116 __DECLARE_8BIT_REGISTER__(SPSR); 00117 __DECLARE_8BIT_REGISTER__(SPCR); 00118 __DECLARE_8BIT_REGISTER__(GPIOR2); 00119 __DECLARE_8BIT_REGISTER__(GPIOR1); 00120 __DECLARE_8BIT_REGISTER__(OCR0B); 00121 __DECLARE_8BIT_REGISTER__(OCR0A); 00122 __DECLARE_8BIT_REGISTER__(TCNT0); 00123 __DECLARE_8BIT_REGISTER__(TCCR0B); 00124 __DECLARE_8BIT_REGISTER__(TCCR0A); 00125 __DECLARE_8BIT_REGISTER__(GTCCR); 00126 __DECLARE_8BIT_REGISTER__(EEARH); 00127 __DECLARE_8BIT_REGISTER__(EEARL); 00128 __DECLARE_8BIT_REGISTER__(EEDR); 00129 __DECLARE_8BIT_REGISTER__(EECR); 00130 __DECLARE_8BIT_REGISTER__(GPIOR0); 00131 __DECLARE_8BIT_REGISTER__(EIFR); 00132 __DECLARE_8BIT_REGISTER__(PCIFR); 00133 __DECLARE_8BIT_REGISTER__(TIFR2); 00134 __DECLARE_8BIT_REGISTER__(TIFR1); 00135 __DECLARE_8BIT_REGISTER__(TIFR0); 00136 __DECLARE_8BIT_REGISTER__(PORTD); 00137 __DECLARE_8BIT_REGISTER__(DDRD); 00138 __DECLARE_8BIT_REGISTER__(PIND); 00139 __DECLARE_8BIT_REGISTER__(PORTC); 00140 __DECLARE_8BIT_REGISTER__(DDRC); 00141 __DECLARE_8BIT_REGISTER__(PINC); 00142 __DECLARE_8BIT_REGISTER__(PORTB); 00143 __DECLARE_8BIT_REGISTER__(DDRB); 00144 __DECLARE_8BIT_REGISTER__(PINB); 00145 __DECLARE_8BIT_REGISTER__(PORTA); 00146 __DECLARE_8BIT_REGISTER__(DDRA); 00147 __DECLARE_16BIT_REGISTER__(OCR1B); 00148 __DECLARE_16BIT_REGISTER__(OCR1A); 00149 __DECLARE_16BIT_REGISTER__(ICR1); 00150 __DECLARE_16BIT_REGISTER__(TCNT1); 00151 __DECLARE_16BIT_REGISTER__(ADC); 00152 __DECLARE_16BIT_REGISTER__(SP); 00153 00154 } // namespace AVRCpp 00155 00156 00157 // UCSR1C 00158 #define _UMSEL11 0x80 00159 #define _UMSEL10 0x40 00160 #define _UPM11 0x20 00161 #define _UPM10 0x10 00162 #define _USBS1 0x8 00163 #define _UCSZ11 0x4 00164 #define _UCSZ10 0x2 00165 #define _UCPOL1 0x1 00166 00167 // UCSR1B 00168 #define _RXCIE1 0x80 00169 #define _TXCIE1 0x40 00170 #define _UDRIE1 0x20 00171 #define _RXEN1 0x10 00172 #define _TXEN1 0x8 00173 #define _UCSZ12 0x4 00174 #define _RXB81 0x2 00175 #define _TXB81 0x1 00176 00177 // UCSR1A 00178 #define _RXC1 0x80 00179 #define _TXC1 0x40 00180 #define _UDRE1 0x20 00181 #define _FE1 0x10 00182 #define _DOR1 0x8 00183 #define _UPE1 0x4 00184 #define _U2X1 0x2 00185 #define _MPCM1 0x1 00186 00187 // UCSR0C 00188 #define _UMSEL01 0x80 00189 #define _UMSEL00 0x40 00190 #define _UPM01 0x20 00191 #define _UPM00 0x10 00192 #define _USBS0 0x8 00193 #define _UCSZ01 0x4 00194 #define _UCSZ00 0x2 00195 #define _UCPOL0 0x1 00196 00197 // UCSR0B 00198 #define _RXCIE0 0x80 00199 #define _TXCIE0 0x40 00200 #define _UDRIE0 0x20 00201 #define _RXEN0 0x10 00202 #define _TXEN0 0x8 00203 #define _UCSZ02 0x4 00204 #define _RXB80 0x2 00205 #define _TXB80 0x1 00206 00207 // UCSR0A 00208 #define _RXC0 0x80 00209 #define _TXC0 0x40 00210 #define _UDRE0 0x20 00211 #define _FE0 0x10 00212 #define _DOR0 0x8 00213 #define _UPE0 0x4 00214 #define _U2X0 0x2 00215 #define _MPCM0 0x1 00216 00217 // TWAMR 00218 #define _TWAM6 0x80 00219 #define _TWAM5 0x40 00220 #define _TWAM4 0x20 00221 #define _TWAM3 0x10 00222 #define _TWAM2 0x8 00223 #define _TWAM1 0x4 00224 #define _TWAM0 0x2 00225 00226 // TWCR 00227 #define _TWINT 0x80 00228 #define _TWEA 0x40 00229 #define _TWSTA 0x20 00230 #define _TWSTO 0x10 00231 #define _TWWC 0x8 00232 #define _TWEN 0x4 00233 #define _TWIE 0x1 00234 00235 // TWAR 00236 #define _TWA6 0x80 00237 #define _TWA5 0x40 00238 #define _TWA4 0x20 00239 #define _TWA3 0x10 00240 #define _TWA2 0x8 00241 #define _TWA1 0x4 00242 #define _TWA0 0x2 00243 #define _TWGCE 0x1 00244 00245 // TWSR 00246 #define _TWS7 0x80 00247 #define _TWS6 0x40 00248 #define _TWS5 0x20 00249 #define _TWS4 0x10 00250 #define _TWS3 0x8 00251 #define _TWPS1 0x2 00252 #define _TWPS0 0x1 00253 00254 // ASSR 00255 #define _EXCLK 0x40 00256 #define _AS2 0x20 00257 #define _TCN2UB 0x10 00258 #define _OCR2AUB 0x8 00259 #define _OCR2BUB 0x4 00260 #define _TCR2AUB 0x2 00261 #define _TCR2BUB 0x1 00262 00263 // TCCR2B 00264 #define _FOC2A 0x80 00265 #define _FOC2B 0x40 00266 #define _WGM22 0x8 00267 #define _CS22 0x4 00268 #define _CS21 0x2 00269 #define _CS20 0x1 00270 00271 // TCCR2A 00272 #define _COM2A1 0x80 00273 #define _COM2A0 0x40 00274 #define _COM2B1 0x20 00275 #define _COM2B0 0x10 00276 #define _WGM21 0x2 00277 #define _WGM20 0x1 00278 00279 // TCCR1C 00280 #define _FOC1A 0x80 00281 #define _FOC1B 0x40 00282 00283 // TCCR1B 00284 #define _ICNC1 0x80 00285 #define _ICES1 0x40 00286 #define _WGM13 0x10 00287 #define _WGM12 0x8 00288 #define _CS12 0x4 00289 #define _CS11 0x2 00290 #define _CS10 0x1 00291 00292 // TCCR1A 00293 #define _COM1A1 0x80 00294 #define _COM1A0 0x40 00295 #define _COM1B1 0x20 00296 #define _COM1B0 0x10 00297 #define _WGM11 0x2 00298 #define _WGM10 0x1 00299 00300 // DIDR1 00301 #define _AIN1D 0x2 00302 #define _AIN0D 0x1 00303 00304 // DIDR0 00305 #define _ADC7D 0x80 00306 #define _ADC6D 0x40 00307 #define _ADC5D 0x20 00308 #define _ADC4D 0x10 00309 #define _ADC3D 0x8 00310 #define _ADC2D 0x4 00311 #define _ADC1D 0x2 00312 #define _ADC0D 0x1 00313 00314 // ADMUX 00315 #define _REFS1 0x80 00316 #define _REFS0 0x40 00317 #define _ADLAR 0x20 00318 #define _MUX4 0x10 00319 #define _MUX3 0x8 00320 #define _MUX2 0x4 00321 #define _MUX1 0x2 00322 #define _MUX0 0x1 00323 00324 // ADCSRB 00325 #define _ACME 0x40 00326 #define _ADTS2 0x4 00327 #define _ADTS1 0x2 00328 #define _ADTS0 0x1 00329 00330 // ADCSRA 00331 #define _ADEN 0x80 00332 #define _ADSC 0x40 00333 #define _ADATE 0x20 00334 #define _ADIF 0x10 00335 #define _ADIE 0x8 00336 #define _ADPS2 0x4 00337 #define _ADPS1 0x2 00338 #define _ADPS0 0x1 00339 00340 // PCMSK3 00341 #define _PCINT31 0x80 00342 #define _PCINT30 0x40 00343 #define _PCINT29 0x20 00344 #define _PCINT28 0x10 00345 #define _PCINT27 0x8 00346 #define _PCINT26 0x4 00347 #define _PCINT25 0x2 00348 #define _PCINT24 0x1 00349 00350 // TIMSK2 00351 #define _OCIE2B 0x4 00352 #define _OCIE2A 0x2 00353 #define _TOIE2 0x1 00354 00355 // TIMSK1 00356 #define _ICIE1 0x20 00357 #define _OCIE1B 0x4 00358 #define _OCIE1A 0x2 00359 #define _TOIE1 0x1 00360 00361 // TIMSK0 00362 #define _OCIE0B 0x4 00363 #define _OCIE0A 0x2 00364 #define _TOIE0 0x1 00365 00366 // PCMSK2 00367 #define _PCINT23 0x80 00368 #define _PCINT22 0x40 00369 #define _PCINT21 0x20 00370 #define _PCINT20 0x10 00371 #define _PCINT19 0x8 00372 #define _PCINT18 0x4 00373 #define _PCINT17 0x2 00374 #define _PCINT16 0x1 00375 00376 // PCMSK1 00377 #define _PCINT15 0x80 00378 #define _PCINT14 0x40 00379 #define _PCINT13 0x20 00380 #define _PCINT12 0x10 00381 #define _PCINT11 0x8 00382 #define _PCINT10 0x4 00383 #define _PCINT9 0x2 00384 #define _PCINT8 0x1 00385 00386 // PCMSK0 00387 #define _PCINT7 0x80 00388 #define _PCINT6 0x40 00389 #define _PCINT5 0x20 00390 #define _PCINT4 0x10 00391 #define _PCINT3 0x8 00392 #define _PCINT2 0x4 00393 #define _PCINT1 0x2 00394 #define _PCINT0 0x1 00395 00396 // EICRA 00397 #define _ISC21 0x20 00398 #define _ISC20 0x10 00399 #define _ISC11 0x8 00400 #define _ISC10 0x4 00401 #define _ISC01 0x2 00402 #define _ISC00 0x1 00403 00404 // PCICR 00405 #define _PCIE3 0x8 00406 #define _PCIE2 0x4 00407 #define _PCIE1 0x2 00408 #define _PCIE0 0x1 00409 00410 // PRR 00411 #define _PRTWI 0x80 00412 #define _PRTIM2 0x40 00413 #define _PRTIM0 0x20 00414 #define _PRUSART1 0x10 00415 #define _PRTIM1 0x8 00416 #define _PRSPI 0x4 00417 #define _PRUSART0 0x2 00418 #define _PRADC 0x1 00419 00420 // CLKPR 00421 #define _CLKPCE 0x80 00422 #define _CLKPS3 0x8 00423 #define _CLKPS2 0x4 00424 #define _CLKPS1 0x2 00425 #define _CLKPS0 0x1 00426 00427 // WDTCSR 00428 #define _WDIF 0x80 00429 #define _WDIE 0x40 00430 #define _WDP3 0x20 00431 #define _WDCE 0x10 00432 #define _WDE 0x8 00433 #define _WDP2 0x4 00434 #define _WDP1 0x2 00435 #define _WDP0 0x1 00436 00437 // SREG 00438 #define _SREG_I 0x80 00439 #define _SREG_T 0x40 00440 #define _SREG_H 0x20 00441 #define _SREG_S 0x10 00442 #define _SREG_V 0x8 00443 #define _SREG_N 0x4 00444 #define _SREG_Z 0x2 00445 #define _SREG_C 0x1 00446 00447 // SPH 00448 #define _SP15 0x80 00449 #define _SP14 0x40 00450 #define _SP13 0x20 00451 #define _SP12 0x10 00452 #define _SP11 0x8 00453 #define _SP10 0x4 00454 #define _SP9 0x2 00455 #define _SP8 0x1 00456 00457 // SPL 00458 #define _SP7 0x80 00459 #define _SP6 0x40 00460 #define _SP5 0x20 00461 #define _SP4 0x10 00462 #define _SP3 0x8 00463 #define _SP2 0x4 00464 #define _SP1 0x2 00465 #define _SP0 0x1 00466 00467 // SPMCSR 00468 #define _SPMIE 0x80 00469 #define _RWWSB 0x40 00470 #define _SIGRD 0x20 00471 #define _RWWSRE 0x10 00472 #define _BLBSET 0x8 00473 #define _PGWRT 0x4 00474 #define _PGERS 0x2 00475 #define _SPMEN 0x1 00476 00477 // MCUCR 00478 #define _JTD 0x80 00479 #define _BODS 0x40 00480 #define _BODSE 0x20 00481 #define _PUD 0x10 00482 #define _IVSEL 0x2 00483 #define _IVCE 0x1 00484 00485 // MCUSR 00486 #define _JTRF 0x10 00487 #define _WDRF 0x8 00488 #define _BORF 0x4 00489 #define _EXTRF 0x2 00490 #define _PORF 0x1 00491 00492 // SMCR 00493 #define _SM2 0x8 00494 #define _SM1 0x4 00495 #define _SM0 0x2 00496 #define _SE 0x1 00497 00498 // ACSR 00499 #define _ACD 0x80 00500 #define _ACBG 0x40 00501 #define _ACO 0x20 00502 #define _ACI 0x10 00503 #define _ACIE 0x8 00504 #define _ACIC 0x4 00505 #define _ACIS1 0x2 00506 #define _ACIS0 0x1 00507 00508 // SPSR 00509 #define _SPIF0 0x80 00510 #define _WCOL0 0x40 00511 #define _SPI2X0 0x1 00512 00513 // SPCR 00514 #define _SPIE0 0x80 00515 #define _SPE0 0x40 00516 #define _DORD0 0x20 00517 #define _MSTR0 0x10 00518 #define _CPOL0 0x8 00519 #define _CPHA0 0x4 00520 #define _SPR01 0x2 00521 #define _SPR00 0x1 00522 00523 // TCCR0B 00524 #define _FOC0A 0x80 00525 #define _FOC0B 0x40 00526 #define _WGM02 0x8 00527 #define _CS02 0x4 00528 #define _CS01 0x2 00529 #define _CS00 0x1 00530 00531 // TCCR0A 00532 #define _COM0A1 0x80 00533 #define _COM0A0 0x40 00534 #define _COM0B1 0x20 00535 #define _COM0B0 0x10 00536 #define _WGM01 0x2 00537 #define _WGM00 0x1 00538 00539 // GTCCR 00540 #define _TSM 0x80 00541 #define _PSR2 0x2 00542 #define _PSR54310 0x1 00543 00544 // EECR 00545 #define _EEPM1 0x20 00546 #define _EEPM0 0x10 00547 #define _EERIE 0x8 00548 #define _EEMPE 0x4 00549 #define _EEPE 0x2 00550 #define _EERE 0x1 00551 00552 // EIFR 00553 #define _INTF2 0x4 00554 #define _INTF1 0x2 00555 #define _INTF0 0x1 00556 00557 // PCIFR 00558 #define _PCIF3 0x8 00559 #define _PCIF2 0x4 00560 #define _PCIF1 0x2 00561 #define _PCIF0 0x1 00562 00563 // TIFR1 00564 #define _ICF1 0x20 00565 #define _OCF1B 0x4 00566 #define _OCF1A 0x2 00567 #define _TOV1 0x1 00568 00569 // TIFR0 00570 #define _OCF0B 0x4 00571 #define _OCF0A 0x2 00572 #define _TOV0 0x1 00573 00574 // PORTD 00575 #define _PD7 0x80 00576 #define _PD6 0x40 00577 #define _PD5 0x20 00578 #define _PD4 0x10 00579 #define _PD3 0x8 00580 #define _PD2 0x4 00581 #define _PD1 0x2 00582 #define _PD0 0x1 00583 00584 // DDRD 00585 #define _DDD7 0x80 00586 #define _DDD6 0x40 00587 #define _DDD5 0x20 00588 #define _DDD4 0x10 00589 #define _DDD3 0x8 00590 #define _DDD2 0x4 00591 #define _DDD1 0x2 00592 #define _DDD0 0x1 00593 00594 // PIND 00595 #define _PIND7 0x80 00596 #define _PIND6 0x40 00597 #define _PIND5 0x20 00598 #define _PIND4 0x10 00599 #define _PIND3 0x8 00600 #define _PIND2 0x4 00601 #define _PIND1 0x2 00602 #define _PIND0 0x1 00603 00604 // PORTC 00605 #define _PC7 0x80 00606 #define _PC6 0x40 00607 #define _PC5 0x20 00608 #define _PC4 0x10 00609 #define _PC3 0x8 00610 #define _PC2 0x4 00611 #define _PC1 0x2 00612 #define _PC0 0x1 00613 00614 // DDRC 00615 #define _DDC7 0x80 00616 #define _DDC6 0x40 00617 #define _DDC5 0x20 00618 #define _DDC4 0x10 00619 #define _DDC3 0x8 00620 #define _DDC2 0x4 00621 #define _DDC1 0x2 00622 #define _DDC0 0x1 00623 00624 // PINC 00625 #define _PINC7 0x80 00626 #define _PINC6 0x40 00627 #define _PINC5 0x20 00628 #define _PINC4 0x10 00629 #define _PINC3 0x8 00630 #define _PINC2 0x4 00631 #define _PINC1 0x2 00632 #define _PINC0 0x1 00633 00634 // PORTB 00635 #define _PB7 0x80 00636 #define _PB6 0x40 00637 #define _PB5 0x20 00638 #define _PB4 0x10 00639 #define _PB3 0x8 00640 #define _PB2 0x4 00641 #define _PB1 0x2 00642 #define _PB0 0x1 00643 00644 // DDRB 00645 #define _DDB7 0x80 00646 #define _DDB6 0x40 00647 #define _DDB5 0x20 00648 #define _DDB4 0x10 00649 #define _DDB3 0x8 00650 #define _DDB2 0x4 00651 #define _DDB1 0x2 00652 #define _DDB0 0x1 00653 00654 // PINB 00655 #define _PINB7 0x80 00656 #define _PINB6 0x40 00657 #define _PINB5 0x20 00658 #define _PINB4 0x10 00659 #define _PINB3 0x8 00660 #define _PINB2 0x4 00661 #define _PINB1 0x2 00662 #define _PINB0 0x1 00663 00664 // PORTA 00665 #define _PA7 0x80 00666 #define _PA6 0x40 00667 #define _PA5 0x20 00668 #define _PA4 0x10 00669 #define _PA3 0x8 00670 #define _PA2 0x4 00671 #define _PA1 0x2 00672 #define _PA0 0x1 00673 00674 // DDRA 00675 #define _DDA7 0x80 00676 #define _DDA6 0x40 00677 #define _DDA5 0x20 00678 #define _DDA4 0x10 00679 #define _DDA3 0x8 00680 #define _DDA2 0x4 00681 #define _DDA1 0x2 00682 #define _DDA0 0x1 00683 00684 00685 // General ports 00686 namespace AVRCpp 00687 { 00688 __DECLARE_PORT__(D); 00689 __DECLARE_PORT__(C); 00690 __DECLARE_PORT__(B); 00691 __DECLARE_PORT__(A); 00692 00693 } // namespace AVRCpp 00694 00695 00696 /**********************************************************************************************************************/ 00697 00698 #endif // ifndef __AVR_CPP_IO_H__ 00699 #endif // ifndef __AVR_CPP_ATMEGA324P_IO_H__
1.5.2
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 MTÜ TTÜ Robotiklubi
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