00001 /**********************************************************************************************************************\ 00002 00003 C++ library for Atmel AVR microcontrollers 00004 Copyright (C) 2007 Lauri Kirikal, Mikk Leini, Rasmus Raag, MTU TTU Robotiklubi 00005 00006 This program is free software; you can redistribute it and/or 00007 modify it under the terms of the GNU General Public License 00008 as published by the Free Software Foundation; either version 2 00009 of the License, or (at your option) any later version. 00010 00011 This program is distributed in the hope that it will be useful, 00012 but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 GNU General Public License for more details. 00015 00016 You should have received a copy of the GNU General Public License 00017 along with this program; if not, write to the Free Software 00018 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 00019 00020 See http://creativecommons.org/licenses/GPL/2.0/ 00021 00022 MTU TTU Robotiklubi http://www.robotiklubi.ee robotiklubi@gmail.com 00023 Lauri Kirikal laurikirikal@gmail.com 00024 Mikk Leini mikk.leini@gmail.com 00025 00026 \**********************************************************************************************************************/ 00027 00028 #ifndef __AVR_CPP_AT90USB1287_IO_H__ 00029 #define __AVR_CPP_AT90USB1287_IO_H__ 00030 00031 #if defined(__DOXYGEN__) && !defined(__AVR_CPP_IO_H__) 00032 #include <avr/cpp/IO.h> 00033 #endif 00034 00035 #ifndef __AVR_CPP_IO_H__ 00036 #error "Include <avr/cpp/IO.h> instead of <avr/cpp/at90usb1287/IO.h>." 00037 #else 00038 00039 00040 /**********************************************************************************************************************\ 00041 00042 at90usb1287 registers, bits and ports declarations. 00043 This file is generated. Do not modify manually. 00044 00045 \**********************************************************************************************************************/ 00046 00047 // Registers 00048 namespace AVRCpp 00049 { 00050 __DECLARE_8BIT_REGISTER__(OTGTCON); 00051 __DECLARE_8BIT_REGISTER__(UPINT); 00052 __DECLARE_8BIT_REGISTER__(UPBCHX); 00053 __DECLARE_8BIT_REGISTER__(UPBCLX); 00054 __DECLARE_8BIT_REGISTER__(UPERRX); 00055 __DECLARE_8BIT_REGISTER__(UEINT); 00056 __DECLARE_8BIT_REGISTER__(UEBCHX); 00057 __DECLARE_8BIT_REGISTER__(UEBCLX); 00058 __DECLARE_8BIT_REGISTER__(UEDATX); 00059 __DECLARE_8BIT_REGISTER__(UEIENX); 00060 __DECLARE_8BIT_REGISTER__(UESTA1X); 00061 __DECLARE_8BIT_REGISTER__(UESTA0X); 00062 __DECLARE_8BIT_REGISTER__(UECFG1X); 00063 __DECLARE_8BIT_REGISTER__(UECFG0X); 00064 __DECLARE_8BIT_REGISTER__(UECONX); 00065 __DECLARE_8BIT_REGISTER__(UERST); 00066 __DECLARE_8BIT_REGISTER__(UENUM); 00067 __DECLARE_8BIT_REGISTER__(UEINTX); 00068 __DECLARE_8BIT_REGISTER__(UDTST); 00069 __DECLARE_8BIT_REGISTER__(UDMFN); 00070 __DECLARE_8BIT_REGISTER__(UDFNUMH); 00071 __DECLARE_8BIT_REGISTER__(UDFNUML); 00072 __DECLARE_8BIT_REGISTER__(UDADDR); 00073 __DECLARE_8BIT_REGISTER__(UDIEN); 00074 __DECLARE_8BIT_REGISTER__(UDINT); 00075 __DECLARE_8BIT_REGISTER__(UDCON); 00076 __DECLARE_8BIT_REGISTER__(OTGINT); 00077 __DECLARE_8BIT_REGISTER__(OTGIEN); 00078 __DECLARE_8BIT_REGISTER__(OTGCON); 00079 __DECLARE_8BIT_REGISTER__(UDPADDH); 00080 __DECLARE_8BIT_REGISTER__(UDPADDL); 00081 __DECLARE_8BIT_REGISTER__(USBINT); 00082 __DECLARE_8BIT_REGISTER__(USBSTA); 00083 __DECLARE_8BIT_REGISTER__(USBCON); 00084 __DECLARE_8BIT_REGISTER__(UHWCON); 00085 __DECLARE_8BIT_REGISTER__(UDR1); 00086 __DECLARE_8BIT_REGISTER__(UBRR1H); 00087 __DECLARE_8BIT_REGISTER__(UBRR1L); 00088 __DECLARE_8BIT_REGISTER__(UCSR1C); 00089 __DECLARE_8BIT_REGISTER__(UCSR1B); 00090 __DECLARE_8BIT_REGISTER__(UCSR1A); 00091 __DECLARE_8BIT_REGISTER__(TWAMR); 00092 __DECLARE_8BIT_REGISTER__(TWCR); 00093 __DECLARE_8BIT_REGISTER__(TWDR); 00094 __DECLARE_8BIT_REGISTER__(TWAR); 00095 __DECLARE_8BIT_REGISTER__(TWSR); 00096 __DECLARE_8BIT_REGISTER__(TWBR); 00097 __DECLARE_8BIT_REGISTER__(ASSR); 00098 __DECLARE_8BIT_REGISTER__(OCR2B); 00099 __DECLARE_8BIT_REGISTER__(OCR2A); 00100 __DECLARE_8BIT_REGISTER__(TCNT2); 00101 __DECLARE_8BIT_REGISTER__(TCCR2B); 00102 __DECLARE_8BIT_REGISTER__(TCCR2A); 00103 __DECLARE_8BIT_REGISTER__(UPDATX); 00104 __DECLARE_8BIT_REGISTER__(UPIENX); 00105 __DECLARE_8BIT_REGISTER__(UPCFG2X); 00106 __DECLARE_8BIT_REGISTER__(UPSTAX); 00107 __DECLARE_8BIT_REGISTER__(UPCFG1X); 00108 __DECLARE_8BIT_REGISTER__(UPCFG0X); 00109 __DECLARE_8BIT_REGISTER__(UPCONX); 00110 __DECLARE_8BIT_REGISTER__(UPRST); 00111 __DECLARE_8BIT_REGISTER__(UPNUM); 00112 __DECLARE_8BIT_REGISTER__(UPINTX); 00113 __DECLARE_8BIT_REGISTER__(UPINRQX); 00114 __DECLARE_8BIT_REGISTER__(UHFLEN); 00115 __DECLARE_8BIT_REGISTER__(UHFNUMH); 00116 __DECLARE_8BIT_REGISTER__(UHFNUML); 00117 __DECLARE_8BIT_REGISTER__(UHADDR); 00118 __DECLARE_8BIT_REGISTER__(UHIEN); 00119 __DECLARE_8BIT_REGISTER__(UHINT); 00120 __DECLARE_8BIT_REGISTER__(UHCON); 00121 __DECLARE_8BIT_REGISTER__(OCR3CH); 00122 __DECLARE_8BIT_REGISTER__(OCR3CL); 00123 __DECLARE_8BIT_REGISTER__(OCR3BH); 00124 __DECLARE_8BIT_REGISTER__(OCR3BL); 00125 __DECLARE_8BIT_REGISTER__(OCR3AH); 00126 __DECLARE_8BIT_REGISTER__(OCR3AL); 00127 __DECLARE_8BIT_REGISTER__(ICR3H); 00128 __DECLARE_8BIT_REGISTER__(ICR3L); 00129 __DECLARE_8BIT_REGISTER__(TCNT3H); 00130 __DECLARE_8BIT_REGISTER__(TCNT3L); 00131 __DECLARE_8BIT_REGISTER__(TCCR3C); 00132 __DECLARE_8BIT_REGISTER__(TCCR3B); 00133 __DECLARE_8BIT_REGISTER__(TCCR3A); 00134 __DECLARE_8BIT_REGISTER__(OCR1CH); 00135 __DECLARE_8BIT_REGISTER__(OCR1CL); 00136 __DECLARE_8BIT_REGISTER__(OCR1BH); 00137 __DECLARE_8BIT_REGISTER__(OCR1BL); 00138 __DECLARE_8BIT_REGISTER__(OCR1AH); 00139 __DECLARE_8BIT_REGISTER__(OCR1AL); 00140 __DECLARE_8BIT_REGISTER__(ICR1H); 00141 __DECLARE_8BIT_REGISTER__(ICR1L); 00142 __DECLARE_8BIT_REGISTER__(TCNT1H); 00143 __DECLARE_8BIT_REGISTER__(TCNT1L); 00144 __DECLARE_8BIT_REGISTER__(TCCR1C); 00145 __DECLARE_8BIT_REGISTER__(TCCR1B); 00146 __DECLARE_8BIT_REGISTER__(TCCR1A); 00147 __DECLARE_8BIT_REGISTER__(DIDR1); 00148 __DECLARE_8BIT_REGISTER__(DIDR0); 00149 __DECLARE_8BIT_REGISTER__(ADMUX); 00150 __DECLARE_8BIT_REGISTER__(ADCSRB); 00151 __DECLARE_8BIT_REGISTER__(ADCSRA); 00152 __DECLARE_8BIT_REGISTER__(ADCH); 00153 __DECLARE_8BIT_REGISTER__(ADCL); 00154 __DECLARE_8BIT_REGISTER__(XMCRB); 00155 __DECLARE_8BIT_REGISTER__(XMCRA); 00156 __DECLARE_8BIT_REGISTER__(TIMSK3); 00157 __DECLARE_8BIT_REGISTER__(TIMSK2); 00158 __DECLARE_8BIT_REGISTER__(TIMSK1); 00159 __DECLARE_8BIT_REGISTER__(TIMSK0); 00160 __DECLARE_8BIT_REGISTER__(PCMSK0); 00161 __DECLARE_8BIT_REGISTER__(EICRB); 00162 __DECLARE_8BIT_REGISTER__(EICRA); 00163 __DECLARE_8BIT_REGISTER__(PCICR); 00164 __DECLARE_8BIT_REGISTER__(OSCCAL); 00165 __DECLARE_8BIT_REGISTER__(PRR1); 00166 __DECLARE_8BIT_REGISTER__(PRR0); 00167 __DECLARE_8BIT_REGISTER__(CLKPR); 00168 __DECLARE_8BIT_REGISTER__(WDTCSR); 00169 __DECLARE_8BIT_REGISTER__(SREG); 00170 __DECLARE_8BIT_REGISTER__(SPH); 00171 __DECLARE_8BIT_REGISTER__(SPL); 00172 __DECLARE_8BIT_REGISTER__(RAMPZ); 00173 __DECLARE_8BIT_REGISTER__(SPMCSR); 00174 __DECLARE_8BIT_REGISTER__(MCUCR); 00175 __DECLARE_8BIT_REGISTER__(MCUSR); 00176 __DECLARE_8BIT_REGISTER__(SMCR); 00177 __DECLARE_8BIT_REGISTER__(OCDR); 00178 __DECLARE_8BIT_REGISTER__(MONDR); 00179 __DECLARE_8BIT_REGISTER__(ACSR); 00180 __DECLARE_8BIT_REGISTER__(SPDR); 00181 __DECLARE_8BIT_REGISTER__(SPSR); 00182 __DECLARE_8BIT_REGISTER__(SPCR); 00183 __DECLARE_8BIT_REGISTER__(GPIOR2); 00184 __DECLARE_8BIT_REGISTER__(GPIOR1); 00185 __DECLARE_8BIT_REGISTER__(PLLCSR); 00186 __DECLARE_8BIT_REGISTER__(OCR0B); 00187 __DECLARE_8BIT_REGISTER__(OCR0A); 00188 __DECLARE_8BIT_REGISTER__(TCNT0); 00189 __DECLARE_8BIT_REGISTER__(TCCR0B); 00190 __DECLARE_8BIT_REGISTER__(TCCR0A); 00191 __DECLARE_8BIT_REGISTER__(GTCCR); 00192 __DECLARE_8BIT_REGISTER__(EEARH); 00193 __DECLARE_8BIT_REGISTER__(EEARL); 00194 __DECLARE_8BIT_REGISTER__(EEDR); 00195 __DECLARE_8BIT_REGISTER__(EECR); 00196 __DECLARE_8BIT_REGISTER__(GPIOR0); 00197 __DECLARE_8BIT_REGISTER__(EIMSK); 00198 __DECLARE_8BIT_REGISTER__(EIFR); 00199 __DECLARE_8BIT_REGISTER__(PCIFR); 00200 __DECLARE_8BIT_REGISTER__(TIFR3); 00201 __DECLARE_8BIT_REGISTER__(TIFR2); 00202 __DECLARE_8BIT_REGISTER__(TIFR1); 00203 __DECLARE_8BIT_REGISTER__(TIFR0); 00204 __DECLARE_8BIT_REGISTER__(PORTF); 00205 __DECLARE_8BIT_REGISTER__(DDRF); 00206 __DECLARE_8BIT_REGISTER__(PINF); 00207 __DECLARE_8BIT_REGISTER__(PORTE); 00208 __DECLARE_8BIT_REGISTER__(DDRE); 00209 __DECLARE_8BIT_REGISTER__(PINE); 00210 __DECLARE_8BIT_REGISTER__(PORTD); 00211 __DECLARE_8BIT_REGISTER__(DDRD); 00212 __DECLARE_8BIT_REGISTER__(PIND); 00213 __DECLARE_8BIT_REGISTER__(PORTC); 00214 __DECLARE_8BIT_REGISTER__(DDRC); 00215 __DECLARE_8BIT_REGISTER__(PINC); 00216 __DECLARE_8BIT_REGISTER__(PORTB); 00217 __DECLARE_8BIT_REGISTER__(DDRB); 00218 __DECLARE_8BIT_REGISTER__(PINB); 00219 __DECLARE_8BIT_REGISTER__(PORTA); 00220 __DECLARE_8BIT_REGISTER__(DDRA); 00221 __DECLARE_8BIT_REGISTER__(PINA); 00222 __DECLARE_16BIT_REGISTER__(UDFNUM); 00223 __DECLARE_16BIT_REGISTER__(UDPADD); 00224 __DECLARE_16BIT_REGISTER__(UHFNUM); 00225 __DECLARE_16BIT_REGISTER__(OCR3C); 00226 __DECLARE_16BIT_REGISTER__(OCR3B); 00227 __DECLARE_16BIT_REGISTER__(OCR3A); 00228 __DECLARE_16BIT_REGISTER__(ICR3); 00229 __DECLARE_16BIT_REGISTER__(TCNT3); 00230 __DECLARE_16BIT_REGISTER__(OCR1C); 00231 __DECLARE_16BIT_REGISTER__(OCR1B); 00232 __DECLARE_16BIT_REGISTER__(OCR1A); 00233 __DECLARE_16BIT_REGISTER__(ICR1); 00234 __DECLARE_16BIT_REGISTER__(TCNT1); 00235 __DECLARE_16BIT_REGISTER__(ADC); 00236 __DECLARE_16BIT_REGISTER__(SP); 00237 00238 } // namespace AVRCpp 00239 00240 00241 // UEIENX 00242 #define _FLERRE 0x80 00243 #define _NAKINE 0x40 00244 #define _NAKOUTE 0x10 00245 #define _RXSTPE 0x8 00246 #define _RXOUTE 0x4 00247 #define _STALLEDE 0x2 00248 #define _TXINE 0x1 00249 00250 // UEINTX 00251 #define _FIFOCON 0x80 00252 #define _NAKINI 0x40 00253 #define _RWAL 0x20 00254 #define _NAKOUTI 0x10 00255 #define _RXSTPI 0x8 00256 #define _RXOUTI 0x4 00257 #define _STALLEDI 0x2 00258 #define _TXINI 0x1 00259 00260 // UCSR1C 00261 #define _UMSEL11 0x80 00262 #define _UMSEL10 0x40 00263 #define _UPM11 0x20 00264 #define _UPM10 0x10 00265 #define _USBS1 0x8 00266 #define _UCSZ11 0x4 00267 #define _UCSZ10 0x2 00268 #define _UCPOL1 0x1 00269 00270 // UCSR1B 00271 #define _RXCIE1 0x80 00272 #define _TXCIE1 0x40 00273 #define _UDRIE1 0x20 00274 #define _RXEN1 0x10 00275 #define _TXEN1 0x8 00276 #define _UCSZ12 0x4 00277 #define _RXB81 0x2 00278 #define _TXB81 0x1 00279 00280 // UCSR1A 00281 #define _RXC1 0x80 00282 #define _TXC1 0x40 00283 #define _UDRE1 0x20 00284 #define _FE1 0x10 00285 #define _DOR1 0x8 00286 #define _UPE1 0x4 00287 #define _U2X1 0x2 00288 #define _MPCM1 0x1 00289 00290 // TWAMR 00291 #define _TWAM6 0x80 00292 #define _TWAM5 0x40 00293 #define _TWAM4 0x20 00294 #define _TWAM3 0x10 00295 #define _TWAM2 0x8 00296 #define _TWAM1 0x4 00297 #define _TWAM0 0x2 00298 00299 // TWCR 00300 #define _TWINT 0x80 00301 #define _TWEA 0x40 00302 #define _TWSTA 0x20 00303 #define _TWSTO 0x10 00304 #define _TWWC 0x8 00305 #define _TWEN 0x4 00306 #define _TWIE 0x1 00307 00308 // TWAR 00309 #define _TWA6 0x80 00310 #define _TWA5 0x40 00311 #define _TWA4 0x20 00312 #define _TWA3 0x10 00313 #define _TWA2 0x8 00314 #define _TWA1 0x4 00315 #define _TWA0 0x2 00316 #define _TWGCE 0x1 00317 00318 // TWSR 00319 #define _TWS7 0x80 00320 #define _TWS6 0x40 00321 #define _TWS5 0x20 00322 #define _TWS4 0x10 00323 #define _TWS3 0x8 00324 #define _TWPS1 0x2 00325 #define _TWPS0 0x1 00326 00327 // ASSR 00328 #define _EXCLK 0x40 00329 #define _AS2 0x20 00330 #define _TCN2UB 0x10 00331 #define _OCR2AUB 0x8 00332 #define _OCR2BUB 0x4 00333 #define _TCR2AUB 0x2 00334 #define _TCR2BUB 0x1 00335 00336 // TCCR2B 00337 #define _FOC2A 0x80 00338 #define _FOC2B 0x40 00339 #define _WGM22 0x8 00340 #define _CS22 0x4 00341 #define _CS21 0x2 00342 #define _CS20 0x1 00343 00344 // TCCR2A 00345 #define _COM2A1 0x80 00346 #define _COM2A0 0x40 00347 #define _COM2B1 0x20 00348 #define _COM2B0 0x10 00349 #define _WGM21 0x2 00350 #define _WGM20 0x1 00351 00352 // UPIENX 00353 #define _FLERRE 0x80 00354 #define _NAKEDE 0x40 00355 #define _PERRE 0x10 00356 #define _TXSTPE 0x8 00357 #define _TXOUTE 0x4 00358 #define _RXSTALLE 0x2 00359 #define _RXINE 0x1 00360 00361 // UPINTX 00362 #define _FIFOCON 0x80 00363 #define _NAKEDI 0x40 00364 #define _RWAL 0x20 00365 #define _PERRI 0x10 00366 #define _TXSTPI 0x8 00367 #define _TXOUTI 0x4 00368 #define _RXSTALLI 0x2 00369 #define _RXINI 0x1 00370 00371 // TCCR3C 00372 #define _FOC3A 0x80 00373 #define _FOC3B 0x40 00374 #define _FOC3C 0x20 00375 00376 // TCCR3B 00377 #define _ICNC3 0x80 00378 #define _ICES3 0x40 00379 #define _WGM33 0x10 00380 #define _WGM32 0x8 00381 #define _CS32 0x4 00382 #define _CS31 0x2 00383 #define _CS30 0x1 00384 00385 // TCCR3A 00386 #define _COM3A1 0x80 00387 #define _COM3A0 0x40 00388 #define _COM3B1 0x20 00389 #define _COM3B0 0x10 00390 #define _COM3C1 0x8 00391 #define _COM3C0 0x4 00392 #define _WGM31 0x2 00393 #define _WGM30 0x1 00394 00395 // TCCR1C 00396 #define _FOC1A 0x80 00397 #define _FOC1B 0x40 00398 #define _FOC1C 0x20 00399 00400 // TCCR1B 00401 #define _ICNC1 0x80 00402 #define _ICES1 0x40 00403 #define _WGM13 0x10 00404 #define _WGM12 0x8 00405 #define _CS12 0x4 00406 #define _CS11 0x2 00407 #define _CS10 0x1 00408 00409 // TCCR1A 00410 #define _COM1A1 0x80 00411 #define _COM1A0 0x40 00412 #define _COM1B1 0x20 00413 #define _COM1B0 0x10 00414 #define _COM1C1 0x8 00415 #define _COM1C0 0x4 00416 #define _WGM11 0x2 00417 #define _WGM10 0x1 00418 00419 // DIDR1 00420 #define _AIN1D 0x2 00421 #define _AIN0D 0x1 00422 00423 // DIDR0 00424 #define _ADC7D 0x80 00425 #define _ADC6D 0x40 00426 #define _ADC5D 0x20 00427 #define _ADC4D 0x10 00428 #define _ADC3D 0x8 00429 #define _ADC2D 0x4 00430 #define _ADC1D 0x2 00431 #define _ADC0D 0x1 00432 00433 // ADMUX 00434 #define _REFS1 0x80 00435 #define _REFS0 0x40 00436 #define _ADLAR 0x20 00437 #define _MUX4 0x10 00438 #define _MUX3 0x8 00439 #define _MUX2 0x4 00440 #define _MUX1 0x2 00441 #define _MUX0 0x1 00442 00443 // ADCSRB 00444 #define _ACME 0x40 00445 #define _MUX5 0x8 00446 #define _ADTS2 0x4 00447 #define _ADTS1 0x2 00448 #define _ADTS0 0x1 00449 00450 // ADCSRA 00451 #define _ADEN 0x80 00452 #define _ADSC 0x40 00453 #define _ADATE 0x20 00454 #define _ADIF 0x10 00455 #define _ADIE 0x8 00456 #define _ADPS2 0x4 00457 #define _ADPS1 0x2 00458 #define _ADPS0 0x1 00459 00460 // XMCRB 00461 #define _XMBK 0x80 00462 #define _XMM2 0x4 00463 #define _XMM1 0x2 00464 #define _XMM0 0x1 00465 00466 // XMCRA 00467 #define _SRE 0x80 00468 #define _SRL2 0x40 00469 #define _SRL1 0x20 00470 #define _SRL0 0x10 00471 #define _SRW11 0x8 00472 #define _SRW10 0x4 00473 #define _SRW01 0x2 00474 #define _SRW00 0x1 00475 00476 // TIMSK3 00477 #define _ICIE3 0x20 00478 #define _OCIE3C 0x8 00479 #define _OCIE3B 0x4 00480 #define _OCIE3A 0x2 00481 #define _TOIE3 0x1 00482 00483 // TIMSK2 00484 #define _OCIE2B 0x4 00485 #define _OCIE2A 0x2 00486 #define _TOIE2 0x1 00487 00488 // TIMSK1 00489 #define _ICIE1 0x20 00490 #define _OCIE1C 0x8 00491 #define _OCIE1B 0x4 00492 #define _OCIE1A 0x2 00493 #define _TOIE1 0x1 00494 00495 // TIMSK0 00496 #define _OCIE0B 0x4 00497 #define _OCIE0A 0x2 00498 #define _TOIE0 0x1 00499 00500 // PCMSK0 00501 #define _PCINT7 0x80 00502 #define _PCINT6 0x40 00503 #define _PCINT5 0x20 00504 #define _PCINT4 0x10 00505 #define _PCINT3 0x8 00506 #define _PCINT2 0x4 00507 #define _PCINT1 0x2 00508 #define _PCINT0 0x1 00509 00510 // EICRB 00511 #define _ISC71 0x80 00512 #define _ISC70 0x40 00513 #define _ISC61 0x20 00514 #define _ISC60 0x10 00515 #define _ISC51 0x8 00516 #define _ISC50 0x4 00517 #define _ISC41 0x2 00518 #define _ISC40 0x1 00519 00520 // EICRA 00521 #define _ISC31 0x80 00522 #define _ISC30 0x40 00523 #define _ISC21 0x20 00524 #define _ISC20 0x10 00525 #define _ISC11 0x8 00526 #define _ISC10 0x4 00527 #define _ISC01 0x2 00528 #define _ISC00 0x1 00529 00530 // PCICR 00531 #define _PCIE0 0x1 00532 00533 // PRR1 00534 #define _PRUSB 0x80 00535 #define _PRTIM3 0x8 00536 #define _PRUSART1 0x1 00537 00538 // PRR0 00539 #define _PRTWI 0x80 00540 #define _PRTIM2 0x40 00541 #define _PRTIM0 0x20 00542 #define _PRTIM1 0x8 00543 #define _PRSPI 0x4 00544 #define _PRADC 0x1 00545 00546 // CLKPR 00547 #define _CLKPCE 0x80 00548 #define _CLKPS3 0x8 00549 #define _CLKPS2 0x4 00550 #define _CLKPS1 0x2 00551 #define _CLKPS0 0x1 00552 00553 // WDTCSR 00554 #define _WDIF 0x80 00555 #define _WDIE 0x40 00556 #define _WDP3 0x20 00557 #define _WDCE 0x10 00558 #define _WDE 0x8 00559 #define _WDP2 0x4 00560 #define _WDP1 0x2 00561 #define _WDP0 0x1 00562 00563 // SREG 00564 #define _SREG_I 0x80 00565 #define _SREG_T 0x40 00566 #define _SREG_H 0x20 00567 #define _SREG_S 0x10 00568 #define _SREG_V 0x8 00569 #define _SREG_N 0x4 00570 #define _SREG_Z 0x2 00571 #define _SREG_C 0x1 00572 00573 // SPH 00574 #define _SP15 0x80 00575 #define _SP14 0x40 00576 #define _SP13 0x20 00577 #define _SP12 0x10 00578 #define _SP11 0x8 00579 #define _SP10 0x4 00580 #define _SP9 0x2 00581 #define _SP8 0x1 00582 00583 // SPL 00584 #define _SP7 0x80 00585 #define _SP6 0x40 00586 #define _SP5 0x20 00587 #define _SP4 0x10 00588 #define _SP3 0x8 00589 #define _SP2 0x4 00590 #define _SP1 0x2 00591 #define _SP0 0x1 00592 00593 // RAMPZ 00594 #define _RAMPZ1 0x2 00595 #define _RAMPZ0 0x1 00596 00597 // SPMCSR 00598 #define _SPMIE 0x80 00599 #define _RWWSB 0x40 00600 #define _SIGRD 0x20 00601 #define _RWWSRE 0x10 00602 #define _BLBSET 0x8 00603 #define _PGWRT 0x4 00604 #define _PGERS 0x2 00605 #define _SPMEN 0x1 00606 00607 // MCUCR 00608 #define _JTD 0x80 00609 #define _PUD 0x10 00610 #define _IVSEL 0x2 00611 #define _IVCE 0x1 00612 00613 // MCUSR 00614 #define _JTRF 0x10 00615 #define _WDRF 0x8 00616 #define _BORF 0x4 00617 #define _EXTRF 0x2 00618 #define _PORF 0x1 00619 00620 // SMCR 00621 #define _SM2 0x8 00622 #define _SM1 0x4 00623 #define _SM0 0x2 00624 #define _SE 0x1 00625 00626 // OCDR 00627 #define _OCDR7 0x80 00628 #define _OCDR6 0x40 00629 #define _OCDR5 0x20 00630 #define _OCDR4 0x10 00631 #define _OCDR3 0x8 00632 #define _OCDR2 0x4 00633 #define _OCDR1 0x2 00634 #define _OCDR0 0x1 00635 00636 // ACSR 00637 #define _ACD 0x80 00638 #define _ACBG 0x40 00639 #define _ACO 0x20 00640 #define _ACI 0x10 00641 #define _ACIE 0x8 00642 #define _ACIC 0x4 00643 #define _ACIS1 0x2 00644 #define _ACIS0 0x1 00645 00646 // SPSR 00647 #define _SPIF 0x80 00648 #define _WCOL 0x40 00649 #define _SPI2X 0x1 00650 00651 // SPCR 00652 #define _SPIE 0x80 00653 #define _SPE 0x40 00654 #define _DORD 0x20 00655 #define _MSTR 0x10 00656 #define _CPOL 0x8 00657 #define _CPHA 0x4 00658 #define _SPR1 0x2 00659 #define _SPR0 0x1 00660 00661 // PLLCSR 00662 #define _PLLP2 0x10 00663 #define _PLLP1 0x8 00664 #define _PLLP0 0x4 00665 #define _PLLE 0x2 00666 #define _PLOCK 0x1 00667 00668 // TCCR0B 00669 #define _FOC0A 0x80 00670 #define _FOC0B 0x40 00671 #define _WGM02 0x8 00672 #define _CS02 0x4 00673 #define _CS01 0x2 00674 #define _CS00 0x1 00675 00676 // TCCR0A 00677 #define _COM0A1 0x80 00678 #define _COM0A0 0x40 00679 #define _COM0B1 0x20 00680 #define _COM0B0 0x10 00681 #define _WGM01 0x2 00682 #define _WGM00 0x1 00683 00684 // GTCCR 00685 #define _TSM 0x80 00686 #define _PSRASY 0x2 00687 #define _PSRSYNC 0x1 00688 00689 // EECR 00690 #define _EEPM1 0x20 00691 #define _EEPM0 0x10 00692 #define _EERIE 0x8 00693 #define _EEMPE 0x4 00694 #define _EEPE 0x2 00695 #define _EERE 0x1 00696 00697 // EIMSK 00698 #define _INT7 0x80 00699 #define _INT6 0x40 00700 #define _INT5 0x20 00701 #define _INT4 0x10 00702 #define _INT3 0x8 00703 #define _INT2 0x4 00704 #define _INT1 0x2 00705 #define _INT0 0x1 00706 00707 // EIFR 00708 #define _INTF7 0x80 00709 #define _INTF6 0x40 00710 #define _INTF5 0x20 00711 #define _INTF4 0x10 00712 #define _INTF3 0x8 00713 #define _INTF2 0x4 00714 #define _INTF1 0x2 00715 #define _INTF0 0x1 00716 00717 // PCIFR 00718 #define _PCIF0 0x1 00719 00720 // TIFR3 00721 #define _ICF3 0x20 00722 #define _OCF3C 0x8 00723 #define _OCF3B 0x4 00724 #define _OCF3A 0x2 00725 #define _TOV3 0x1 00726 00727 // TIFR2 00728 #define _OCF2B 0x4 00729 #define _OCF2A 0x2 00730 #define _TOV2 0x1 00731 00732 // TIFR1 00733 #define _ICF1 0x20 00734 #define _OCF1C 0x8 00735 #define _OCF1B 0x4 00736 #define _OCF1A 0x2 00737 #define _TOV1 0x1 00738 00739 // TIFR0 00740 #define _OCF0B 0x4 00741 #define _OCF0A 0x2 00742 #define _TOV0 0x1 00743 00744 // PORTF 00745 #define _PF7 0x80 00746 #define _PF6 0x40 00747 #define _PF5 0x20 00748 #define _PF4 0x10 00749 #define _PF3 0x8 00750 #define _PF2 0x4 00751 #define _PF1 0x2 00752 #define _PF0 0x1 00753 00754 // DDRF 00755 #define _DDF7 0x80 00756 #define _DDF6 0x40 00757 #define _DDF5 0x20 00758 #define _DDF4 0x10 00759 #define _DDF3 0x8 00760 #define _DDF2 0x4 00761 #define _DDF1 0x2 00762 #define _DDF0 0x1 00763 00764 // PINF 00765 #define _PINF7 0x80 00766 #define _PINF6 0x40 00767 #define _PINF5 0x20 00768 #define _PINF4 0x10 00769 #define _PINF3 0x8 00770 #define _PINF2 0x4 00771 #define _PINF1 0x2 00772 #define _PINF0 0x1 00773 00774 // PORTE 00775 #define _PE7 0x80 00776 #define _PE6 0x40 00777 #define _PE5 0x20 00778 #define _PE4 0x10 00779 #define _PE3 0x8 00780 #define _PE2 0x4 00781 #define _PE1 0x2 00782 #define _PE0 0x1 00783 00784 // DDRE 00785 #define _DDE7 0x80 00786 #define _DDE6 0x40 00787 #define _DDE5 0x20 00788 #define _DDE4 0x10 00789 #define _DDE3 0x8 00790 #define _DDE2 0x4 00791 #define _DDE1 0x2 00792 #define _DDE0 0x1 00793 00794 // PINE 00795 #define _PINE7 0x80 00796 #define _PINE6 0x40 00797 #define _PINE5 0x20 00798 #define _PINE4 0x10 00799 #define _PINE3 0x8 00800 #define _PINE2 0x4 00801 #define _PINE1 0x2 00802 #define _PINE0 0x1 00803 00804 // PORTD 00805 #define _PD7 0x80 00806 #define _PD6 0x40 00807 #define _PD5 0x20 00808 #define _PD4 0x10 00809 #define _PD3 0x8 00810 #define _PD2 0x4 00811 #define _PD1 0x2 00812 #define _PD0 0x1 00813 00814 // DDRD 00815 #define _DDD7 0x80 00816 #define _DDD6 0x40 00817 #define _DDD5 0x20 00818 #define _DDD4 0x10 00819 #define _DDD3 0x8 00820 #define _DDD2 0x4 00821 #define _DDD1 0x2 00822 #define _DDD0 0x1 00823 00824 // PIND 00825 #define _PIND7 0x80 00826 #define _PIND6 0x40 00827 #define _PIND5 0x20 00828 #define _PIND4 0x10 00829 #define _PIND3 0x8 00830 #define _PIND2 0x4 00831 #define _PIND1 0x2 00832 #define _PIND0 0x1 00833 00834 // PORTC 00835 #define _PC7 0x80 00836 #define _PC6 0x40 00837 #define _PC5 0x20 00838 #define _PC4 0x10 00839 #define _PC3 0x8 00840 #define _PC2 0x4 00841 #define _PC1 0x2 00842 #define _PC0 0x1 00843 00844 // DDRC 00845 #define _DDC7 0x80 00846 #define _DDC6 0x40 00847 #define _DDC5 0x20 00848 #define _DDC4 0x10 00849 #define _DDC3 0x8 00850 #define _DDC2 0x4 00851 #define _DDC1 0x2 00852 #define _DDC0 0x1 00853 00854 // PINC 00855 #define _PINC7 0x80 00856 #define _PINC6 0x40 00857 #define _PINC5 0x20 00858 #define _PINC4 0x10 00859 #define _PINC3 0x8 00860 #define _PINC2 0x4 00861 #define _PINC1 0x2 00862 #define _PINC0 0x1 00863 00864 // PORTB 00865 #define _PB7 0x80 00866 #define _PB6 0x40 00867 #define _PB5 0x20 00868 #define _PB4 0x10 00869 #define _PB3 0x8 00870 #define _PB2 0x4 00871 #define _PB1 0x2 00872 #define _PB0 0x1 00873 00874 // DDRB 00875 #define _DDB7 0x80 00876 #define _DDB6 0x40 00877 #define _DDB5 0x20 00878 #define _DDB4 0x10 00879 #define _DDB3 0x8 00880 #define _DDB2 0x4 00881 #define _DDB1 0x2 00882 #define _DDB0 0x1 00883 00884 // PINB 00885 #define _PINB7 0x80 00886 #define _PINB6 0x40 00887 #define _PINB5 0x20 00888 #define _PINB4 0x10 00889 #define _PINB3 0x8 00890 #define _PINB2 0x4 00891 #define _PINB1 0x2 00892 #define _PINB0 0x1 00893 00894 // PORTA 00895 #define _PA7 0x80 00896 #define _PA6 0x40 00897 #define _PA5 0x20 00898 #define _PA4 0x10 00899 #define _PA3 0x8 00900 #define _PA2 0x4 00901 #define _PA1 0x2 00902 #define _PA0 0x1 00903 00904 // DDRA 00905 #define _DDA7 0x80 00906 #define _DDA6 0x40 00907 #define _DDA5 0x20 00908 #define _DDA4 0x10 00909 #define _DDA3 0x8 00910 #define _DDA2 0x4 00911 #define _DDA1 0x2 00912 #define _DDA0 0x1 00913 00914 // PINA 00915 #define _PINA7 0x80 00916 #define _PINA6 0x40 00917 #define _PINA5 0x20 00918 #define _PINA4 0x10 00919 #define _PINA3 0x8 00920 #define _PINA2 0x4 00921 #define _PINA1 0x2 00922 #define _PINA0 0x1 00923 00924 00925 // General ports 00926 namespace AVRCpp 00927 { 00928 __DECLARE_PORT__(F); 00929 __DECLARE_PORT__(E); 00930 __DECLARE_PORT__(D); 00931 __DECLARE_PORT__(C); 00932 __DECLARE_PORT__(B); 00933 __DECLARE_PORT__(A); 00934 00935 } // namespace AVRCpp 00936 00937 00938 /**********************************************************************************************************************/ 00939 00940 #endif // ifndef __AVR_CPP_IO_H__ 00941 #endif // ifndef __AVR_CPP_AT90USB1287_IO_H__
1.5.2
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 MTÜ TTÜ Robotiklubi
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